// fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
// using a 33Mhz clock,
- // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1
- sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
+ // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
+ // using a 100Mhz clock,
+ // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
+ sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
sasc_top sasc_top(clk, !rst_in,
uart_in,
uart_out,