migrate verilog into ship files

[fleet.git] / ships / Execute.ship

diff --git a/ships/Execute.ship b/ships/Execute.ship
index 0946121..a50b463 100644 (file)
--- a/ships/Execute.ship
+++ b/ships/Execute.ship
@@ -12,6 +12,54 @@ data  in:   in
 
 == ArchSim ==============================================================
 == FPGA ==============================================================
+`include "macros.v"
+
+module execute (clk, command_r,   command_a_, command_d,
+                     ihorn_r_, ihorn_a, ihorn_d_,
+                     dhorn_r_, dhorn_a, dhorn_d_
+               );
+  input clk;
+
+  `input(command_r,   command_a,   command_a_, [(`DATAWIDTH-1):0], command_d)
+  `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
+  `defreg(ihorn_d_,                   [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+  `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
+  `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0], dhorn_d)
+
+  reg ihorn_full;
+  reg dhorn_full;
+
+  always @(posedge clk) begin
+    if (ihorn_full) begin
+      `onwrite(ihorn_r, ihorn_a)
+        ihorn_full = 0;
+      end
+    end else if (dhorn_full) begin
+      `onwrite(dhorn_r, dhorn_a)
+        dhorn_full = 0;
+      end
+    end else begin
+      `onread(command_r, command_a)
+        case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+          0: begin
+              ihorn_full  = 1;
+              ihorn_d = command_d;
+              end
+          //01:
+          2: begin
+              dhorn_full  = 1;
+              `packet_data(dhorn_d) = command_d[23:0];
+              `packet_dest(dhorn_d) = command_d[34:24];
+              end
+          //11:
+        endcase
+      end
+    end
+  end
+
+
+endmodule
+
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>