migrate verilog into ship files

[fleet.git] / ships / Fifo.ship

diff --git a/ships/Fifo.ship b/ships/Fifo.ship
index 8c96494..f4d8ea1 100644 (file)
--- a/ships/Fifo.ship
+++ b/ships/Fifo.ship
@@ -19,6 +19,31 @@ data  out:  out
 
 == ArchSim ==============================================================
 == FPGA ==============================================================
+`include "macros.v"
+
+// fifo *ship*: a 16-deep word-wide fifo
+module fifo (clk, 
+             in_r,  in_a, in_d,
+             out_r, out_a, out_d);
+
+  input  clk;
+  input  in_r;
+  input  out_a;
+  output in_a;
+  output out_r;
+  input  [(`DATAWIDTH-1):0] in_d;
+  output [(`DATAWIDTH-1):0] out_d;
+
+  wire   [(`DATAWIDTH-1):0] d12;
+  wire   [(`DATAWIDTH-1):0] d23;
+  wire   [(`DATAWIDTH-1):0] d34;
+
+  fifo4 s1(clk, in_r, in_a, in_d, r12, a12,     d12);
+  fifo4 s2(clk, r12,  a12,  d12,  r23, a23,     d23);
+  fifo4 s3(clk, r23,  a23,  d23,  r34, a34,     d34);
+  fifo4 s4(clk, r34,  a34,  d34,  out_r, out_a, out_d);
+
+endmodule
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>