== TeX ==============================================================
== ArchSim ==============================================================
== FPGA ==============================================================
+`include "macros.v"
+`define BRAM_ADDR_WIDTH 14
+`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
+`define BRAM_NAME iscratch_bram
+`include "bram.inc"
+
+module iscratch (clk,
+ write_addr_r, write_addr_a_, write_addr_d,
+ write_data_r, write_data_a_, write_data_d,
+ write_done_r_, write_done_a, write_done_d_,
+ cbd_r, cbd_a_, cbd_d,
+ preload_r, preload_a_, preload_d,
+ ihorn_r_, ihorn_a, ihorn_d_,
+ dhorn_r_, dhorn_a, dhorn_d_
+ );
+
+ input clk;
+ `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
+ `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
+ `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
+ `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
+
+ `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
+ `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
+ `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
+ `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+ `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
+ `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
+
+ reg ihorn_full;
+ initial ihorn_full = 0;
+ reg dhorn_full;
+ initial dhorn_full = 0;
+ reg command_valid;
+ initial command_valid = 0;
+
+ reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
+ reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
+ initial preload_size = 0;
+
+ reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
+ reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
+ reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
+ reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
+ reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
+ reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
+ reg [(`INSTRUCTION_WIDTH-1):0] command;
+ reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
+ reg send_done;
+
+ reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
+ reg [(`DATAWIDTH-1):0] data;
+
+ reg write_flag;
+ reg [(`BRAM_ADDR_WIDTH-1):0] write_addr;
+ reg [(`BRAM_DATA_WIDTH-1):0] write_data;
+
+ wire [(`BRAM_DATA_WIDTH-1):0] ramread;
+
+ reg command_valid_read;
+ initial command_valid_read = 0;
+
+ reg launched;
+ initial launched = 0;
+
+ iscratch_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread);
+
+ always @(posedge clk) begin
+
+ write_flag <= 0;
+
+ if (!write_addr_r && write_addr_a) write_addr_a = 0;
+ if (!write_data_r && write_data_a) write_data_a = 0;
+
+ if (command_valid_read) begin
+ command_valid_read <= 0;
+ command_valid <= 1;
+
+ end else if (send_done) begin
+ `onwrite(write_done_r, write_done_a)
+ send_done <= 0;
+ end
+
+ end else if (write_addr_r && write_data_r) begin
+ write_addr_a = 1;
+ write_data_a = 1;
+ send_done <= 1;
+ write_flag <= 1;
+ write_addr <= write_addr_d;
+ write_data <= write_data_d;
+
+ end else if (ihorn_full && launched) begin
+ `onwrite(ihorn_r, ihorn_a)
+ ihorn_full <= 0;
+ end
+
+ end else if (dhorn_full) begin
+ `onwrite(dhorn_r, dhorn_a)
+ dhorn_full <= 0;
+ end
+
+ end else if (command_valid) begin
+ command_valid <= 0;
+ command = ramread;
+ case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+ 0: begin
+ ihorn_full <= 1;
+ ihorn_d <= command;
+ end
+ 1: begin
+ dhorn_full <= 1;
+ temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
+ temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
+ data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
+ data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
+ `packet_data(dhorn_d) <= temp;
+ `packet_dest(dhorn_d) <=
+ command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
+ end
+ 2: begin
+ dhorn_full <= 1;
+ `packet_data(dhorn_d) <= command[23:0];
+ `packet_dest(dhorn_d) <= command[34:24];
+ end
+ 3: begin
+ dhorn_full <= 1;
+ `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from;
+ `packet_dest(dhorn_d) <= command[34:24];
+ end
+ endcase
+
+ end else if (cbd_pos < cbd_size) begin
+ current_instruction_read_from <= cbd_base+cbd_pos;
+ command_valid_read <= 1;
+ cbd_pos <= cbd_pos + 1;
+
+ end else begin
+ `onread(cbd_r, cbd_a)
+ cbd_pos <= 0;
+ cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
+ cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
+
+ end else begin
+ `onread(preload_r, preload_a)
+ if (preload_size == 0) begin
+ preload_size <= preload_d;
+ end else if (!launched) begin
+ write_flag <= 1;
+ write_data <= preload_d;
+ write_addr <= preload_pos;
+ if (preload_pos == 0) begin
+ temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
+ temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
+ end
+ if ((preload_pos+1) == preload_size) begin
+ cbd_pos <= 0;
+ cbd_base <= temp_base;
+ cbd_size <= temp_size;
+ launched <= 1;
+ end
+ preload_pos <= preload_pos + 1;
+ end
+ end
+ end
+ end
+ end
+endmodule
+
+
+
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
projects / fleet.git / blobdiff