migrate verilog into ship files

[fleet.git] / ships / Lut.ship

diff --git a/ships/Lut.ship b/ships/Lut.ship
index e920c9d..2f18657 100644 (file)
--- a/ships/Lut.ship
+++ b/ships/Lut.ship
@@ -26,6 +26,7 @@ data  out:  out
 
 == ArchSim ==============================================================
 == FPGA ==============================================================
+// not implemented FIXME
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>