== TeX ==============================================================
-This ship implements a 3-input {\bf L}ook {\bf U}p {\bf T}able. The
-least significant eight bits of the {\tt inLut} value form a truth
-table with three inputs and one output.
+This ship implements a bitwise 3-input {\bf L}ook {\bf U}p {\bf
+T}able. The least significant eight bits of the {\tt inLut} value
+form a truth table with three inputs and one output.
When values are available at all four inputs they are consumed and a
value is produced at {\tt out}. Each bit of {\tt out} is produced by
as a bit index into {\tt inLut}'s value (whose least significant bit
is considered ``bit zero'').
-The ship-specific constants refer to commonly-used truth tables for
-{\it two-input} functions; these constant truth tables are invariant
-under input {\tt in3}.
== Fleeterpreter ====================================================
public void service() {
if (box_in1.dataReadyForShip() &&
box_in2.dataReadyForShip() &&
box_in3.dataReadyForShip() &&
- box_inLut.dataReadyForShip()) {
+ box_inLut.dataReadyForShip() &&
+ box_out.readyForDataFromShip()) {
long a = box_in1.removeDataForShip();
long b = box_in2.removeDataForShip();
long c = box_in3.removeDataForShip();
genvar i;
generate
for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
- assign out[i] = inLut_d[{in3_d[i], in2_d[i], in1_d[i]}];
+ assign out[i] = reg_inLut[{reg_in3[i], reg_in2[i], reg_in1[i]}];
end
endgenerate
always @(posedge clk) begin
if (!have_in1) begin
`onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
- end
+ end else
if (!have_in2) begin
`onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
- end
+ end else
if (!have_in3) begin
`onread(in3_r, in3_a) have_in3 = 1; reg_in3 = in3_d; end
- end
+ end else
if (!have_inLut) begin
`onread(inLut_r, inLut_a) have_inLut = 1; reg_inLut = inLut_d; end
- end
+ end else
if (have_in1 && have_in2 && have_in3 && have_inLut) begin
out_d = out;
#ship lut : Lut3
#ship alu : Alu1
-// constant inputs
-85: sendto lut.in1;
-51: sendto lut.in2;
-15: sendto lut.in3;
-
-lut.in1: take; [*] deliver;
-lut.in2: take; [*] deliver;
-lut.in3: take; [*] deliver;
-lut.inLut: [*] take, deliver;
+lut.in1: literal 85; [*] deliver;
+lut.in2: literal 51; [*] deliver;
+lut.in3: literal 15; [*] deliver;
lut.out: [*] take, sendto debug.in;
// cycle through truth tables using alu as INC
-1: sendto alu.inOp;
alu.inOp:
- take;
- [120] deliver;
- [120] deliver;
- [15] deliver;
-alu.in: [*] take, deliver;
-0: sendto alu.in;
+ literal 1;
+ load repeat counter with 63;
+ deliver;
+ load repeat counter with 63;
+ deliver;
+ load repeat counter with 63;
+ deliver;
+ load repeat counter with 63;
+ deliver;
+ load repeat counter with 3;
+ deliver;
+alu.in:
+ literal 0;
+ deliver;
+ [*] take, deliver;
alu.out:
- [*] nop;
- (*) wait, take, sendto lut.inLut;
- (*) sendto alu.in;
- kill;
+ clog;
+ load loop counter with 2;
+ wait, take, sendto lut.inLut;
+ sendto alu.in;
+ unclog;
// acks from debug ship trigger new truth tables
-debug.in: [*] take, deliver, notify alu.out;
+debug.in:
+ [*] take, deliver, notify alu.out;
-// kickoff
-0: sendto lut.inLut;
+lut.inLut:
+ literal 0;
+ deliver;
+ [*] take, deliver;