40nm omega counter: switch design to use a timing constraint.

[fleet.git] / ships / Lut3.ship

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index 17063d8..a85b8f3 100644 (file)
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -75,7 +75,7 @@ is considered ``bit zero'').
   assign lut = inLut_d[7:0];
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
       out_draining <= 0;
     end else begin
@@ -376,8 +376,8 @@ alu.in1:
 alu.out:
   set olc=2;
   head;
-  [Rq] recv token, collect, send to lut.inLut;
-  [Rq] send to alu.in1;
+  recv token, collect, send to lut.inLut;
+  send to alu.in1;
   tail;
 
 lut.inLut: