== FleetSim ==============================================================
== FPGA ==============================================================
+ reg out_draining;
wire [7:0] lut;
genvar i;
assign lut = inLut_d[7:0];
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
`reset
+ out_draining <= 0;
end else begin
- `flush
`cleanup
- if (`out_draining) begin
+ if (out_draining && `out_empty) begin
`drain_in1
`drain_in2
`drain_in3
`drain_inLut
+ out_draining <= 0;
end
- if (`in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+ if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
`fill_out
+ out_draining <= 1;
end
end
end
set ilc=*; recv, deliver;
alu.out:
set olc=2;
- [Rq] recv token, collect, send to lut.inLut;
- [Rq] send to alu.in1;
+ head;
+ recv token, collect, send to lut.inLut;
+ send to alu.in1;
tail;
lut.inLut: