data in: inAddrRead
data in: inAddrWrite
data in: inDataWrite
-data in: inStride
-data in: inCount
data out: out
-data out: outIhorn
== TeX ==============================================================
The {\tt Memory} ship represents an interface to a storage space,
which can be used to read from it or write to it. This storage space
-might be a fast on-chip cache, off chip DRAM, or perhaps even a disk drive.
+might be a fast on-chip cache, off chip DRAM, or perhaps even a disk
+drive.
+
+Generally, distinct {\tt Memory} ships do not access the same backing
+storage, although this is not strictly prohibited.
+
+Each {\tt Memory} ship may have multiple {\it interfaces}, numbered
+starting with {\tt 0}. Each interface may have any subset of the
+following docks: {\tt inCBD}, {\tt inAddrRead}, {\tt inAddrWrite},
+{\tt inDataWrite}, and {\tt out}. If {\tt inCBD} or {\tt inAddrRead}
+is present on an interface, then {\tt out} must be present as well.
+If {\tt inAddrWrite} is present then {\tt inDataWrite} must be present
+as well.
+
+Each interface serializes the operations presented to it; this means
+that an interface with both read and write capabilities will not be
+able to read and write concurrently. Instead, a {\tt Memory} ship
+with the ability to read and write concurrently should have two
+interfaces, one which is read-only and one which is write-only.
There may be multiple {\tt Memory} ships which interface to the same
physical storage space. An implementation of Fleet must provide
\subsection*{Reading}
When a word is delivered to {\tt inAddrRead}, the word residing in
-memory at that address is provided at {\tt out}.
+memory at that address is provided at {\tt out}. The {\tt c-flag} at
+the {\tt out} port is set to zero.
\subsection*{Writing}
the word at {\tt inDataWrite} is written to the address specified by
{\tt inAddrWrite}. Once the word is successfully committed to memory,
the value {\tt inAddr+inStride} is provided at {\tt out} (that is, the
-address of the next word to be written).
+address of the next word to be written). The {\tt c-flag} at
+the {\tt out} port is set to one.
\subsection*{To Do}
}
mem[addr] = val;
}
-/*
- public void dispatch(int addr, int size) {
- for(int i=addr; i<addr+size; i++) {
- Instruction instr = ((Interpreter)getFleet()).readInstruction(getFleet().getUniversalSource(), readMem(i));
- ((Interpreter)getFleet()).dispatch(instr, i);
- }
- }
-
- public void boot(byte[] instructions) {
- Interpreter fleet = (Interpreter)getFleet();
- // load the iscratch and take note of the 0-address INCBD
- long launch = 0;
- for(int i=0; i<instructions.length; i+=6) {
- long word = 0;
- for(int j=0; j<6; j++)
- word = (word << 8) | (instructions[i+j] & 0xff);
- writeMem(i/6, word);
- if (i==0) launch = word;
- }
-
- // dispatch the 0-address INCBD
- int base = (int)(launch >> 6);
- base = base & ~(0xffffffff << 18);
- int size = (int)launch;
- size = size & ~(0xffffffff << 6);
- dispatch(base, size);
+ private Queue<Long> toDispatch = new LinkedList<Long>();
+ public void reset() {
+ super.reset();
+ mem = new long[0];
+ toDispatch.clear();
}
-*/
- private long stride = 0;
- private long count = 0;
- private long addr = 0;
- private boolean writing = false;
-
public void service() {
-/*
+ if (toDispatch.size() > 0) {
+ if (!box_out.readyForDataFromShip()) return;
+ box_out.addDataFromShip(toDispatch.remove());
+ }
if (box_inCBD.dataReadyForShip()) {
long val = box_inCBD.removeDataForShip();
- long addr = val >> 6;
- long size = val & 0x3f;
- dispatch((int)addr, (int)size);
- }
-*/
- if (count > 0) {
- if (writing) {
- if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
- writeMem((int)addr, box_inDataWrite.removeDataForShip());
- box_out.addDataFromShip(0);
- count--;
- addr += stride;
- }
- } else {
- if (box_out.readyForDataFromShip()) {
- box_out.addDataFromShip(readMem((int)addr));
- count--;
- addr += stride;
- }
- }
-
- } else if (box_inAddrRead.dataReadyForShip()) {
- addr = box_inAddrRead.removeDataForShip();
- stride = 0;
- count = 1;
- writing = false;
-
- } else if (box_inAddrWrite.dataReadyForShip()) {
- addr = box_inAddrWrite.peekPacketForShip().value;
- box_inAddrWrite.removeDataForShip();
- stride = 0;
- count = 1;
- writing = true;
+ long addr = ((Interpreter)getFleet()).CBD_OFFSET.getval(val);
+ long size = ((Interpreter)getFleet()).CBD_SIZE.getval(val);
+ for(int i=0; i<size; i++)
+ toDispatch.add(readMem((int)(addr+i)));
+ } else if (box_inAddrWrite.dataReadyForShip() && box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
+ writeMem((int)box_inAddrWrite.removeDataForShip(), box_inDataWrite.removeDataForShip());
+ box_out.addDataFromShip(0,true);
+ } else if (box_inAddrRead.dataReadyForShip() && box_out.readyForDataFromShip()) {
+ box_out.addDataFromShip(readMem((int)box_inAddrRead.removeDataForShip()),false);
}
}
== FPGA ==============================================================
- reg [(`CODEBAG_SIZE_BITS-1):0] cursor;
- reg write_flag;
+ `define BRAM_ADDR_WIDTH 14
+ `define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))
- wire [(`BRAM_ADDR_WIDTH-1):0] addr1;
- wire [(`BRAM_ADDR_WIDTH-1):0] addr2;
- wire [(`BRAM_DATA_WIDTH-1):0] val2;
- assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0];
- assign addr2 = (inCBD_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)])+cursor;
+ reg [(`WORDWIDTH-1):0] ram [((`BRAM_SIZE)-1):0];
+ reg [(`BRAM_ADDR_WIDTH-1):0] addr1;
+ reg [(`BRAM_ADDR_WIDTH-1):0] addr2;
+ reg [(`WORDWIDTH-1):0] out1;
+ reg [(`WORDWIDTH-1):0] out2;
- bram14 mybram(clk, rst, write_flag, addr1, addr2, inDataWrite_d, out_d_, val2);
+ reg out_w;
+ reg write_flag;
+ reg [(`BRAM_ADDR_WIDTH-1):0] cursor;
+ reg [(`CODEBAG_SIZE_BITS-1):0] counter;
- always @(posedge clk) begin
+ assign out_d_ = { out_w, out1 };
- write_flag <= 0;
+ // I use "blocking assignment" here in order to facilitate BRAM inference
+ always @(posedge clk) begin
+ write_flag = 0;
- if (!rst) begin
+ if (rst) begin
`reset
- cursor <= 0;
+ cursor = 0;
+ counter = 0;
end else begin
- write_flag <= 0;
-
- if (!inAddrRead_r && inAddrRead_a) inAddrRead_a <= 0;
- if (!inDataWrite_r && inDataWrite_a) inDataWrite_a <= 0;
- if (!inAddrWrite_r && inAddrWrite_a) inAddrWrite_a <= 0;
-
- if ( out_r && !out_a) begin
- end else if ( out_r && out_a) begin out_r <= 0;
- end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
- inAddrRead_a <= 1;
- out_r <= 1;
-
- end else if (!out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
- // timing note: it's okay to set the *_a flags here because *_d will still
- // be valid on the *next* cycle, which is all we care about
- inAddrWrite_a <= 1;
- inDataWrite_a <= 1;
- out_r <= 1;
- write_flag <= 1;
-
- end else if ( outIhorn_r && outIhorn_a) begin outIhorn_r <= 0;
- end else if (!inCBD_r && inCBD_a) begin inCBD_a <= 0;
- end else if ( inCBD_r && !inCBD_a && !outIhorn_r && !outIhorn_a) begin
- if (cursor < inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
- outIhorn_d <= val2;
- outIhorn_r <= 1;
- cursor <= cursor + 1;
- end else begin
- inCBD_a <= 1;
- cursor <= 0;
+ `cleanup
+
+ if (counter!=0) begin
+ if (`out_empty) begin
+ `fill_out
+ out_w = 0;
+ addr1 = cursor;
+ cursor = cursor + 1;
+ counter = counter - 1;
end
+
+ end else if (`inCBD_full) begin
+ cursor = inCBD_d[(`WORDWIDTH-1):(`CODEBAG_SIZE_BITS)];
+ counter = inCBD_d[(`CODEBAG_SIZE_BITS-1):0];
+ addr1 = cursor;
+ `drain_inCBD
+
+ end else if (`out_empty && `inAddrRead_full) begin
+ addr1 = inAddrRead_d[(`WORDWIDTH-1):0];
+ `drain_inAddrRead
+ `fill_out
+ out_w = 0;
+
+ end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full) begin
+ write_flag = 1;
+ `drain_inAddrWrite
+ `drain_inDataWrite
+ `fill_out
+ addr2 = inAddrWrite_d[(`WORDWIDTH-1):0];
+ out_w = 1;
+
end
end
+
+ // this must appear at the end of the block, outside of any if..then's
+ if (write_flag)
+ ram[addr2] <= inDataWrite_d;
+ out1 <= ram[addr1];
+ out2 <= ram[addr2];
end
== Test ==============================================================
+// Note: this only tests the read/write interfaces, not the inCBD interface
+// FIXME: test c-flag at out dock
+
// expected output
-#expect 12
-#expect 13
-#expect 14
+#expect 10
// ships required in order to run this code
#ship debug : Debug
#ship memory : Memory
-// instructions not in any codebag are part of the "root codebag"
-// which is dispatched when the code is loaded
+memory.inAddrWrite:
+ set word=3;
+ deliver;
+ deliver;
-memory.inCBD:
- literal BOB;
+memory.inDataWrite:
+ set word=4;
+ deliver;
+ set word=10;
deliver;
-BOB: {
- debug.in:
- literal 12; deliver;
- literal 13; deliver;
- literal 14; deliver;
-}
+memory.inAddrRead:
+ recv token;
+ set word=3;
+ deliver;
+
+memory.out:
+ collect;
+ collect;
+ send token to memory.inAddrRead;
+ collect;
+ send to debug.in;
+
+debug.in:
+ set ilc=*;
+ recv, deliver;
== Constants ========================================================
projects / fleet.git / blobdiff