migrate verilog into ship files

[fleet.git] / ships / Shift.ship

diff --git a/ships/Shift.ship b/ships/Shift.ship
index 8450c78..dfba5e1 100644 (file)
--- a/ships/Shift.ship
+++ b/ships/Shift.ship
@@ -20,6 +20,7 @@ data out: out
 
 == ArchSim ==============================================================
 == FPGA ==============================================================
+// not implemented FIXME!
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>