data in: inY
data in: inData
+percolate up: vga_psave 1
+percolate up: vga_hsync 1
+percolate up: vga_vsync 1
+percolate up: vga_sync 1
+percolate up: vga_blank 1
+percolate up: vga_r 8
+percolate up: vga_g 8
+percolate up: vga_b 8
+percolate up: vga_clkout 1
+
== TeX ==============================================================
== Fleeterpreter ====================================================
== FPGA ==============================================================
+ wire vga_clk_unbuffered; // synthesis attribute period of vga_clk_unbuffered is "40 ns";
+
+ wire vga_clk;
+ wire vga_clk_fb;
+
+ BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
+ DCM // 25Mhz VGA clock
+ #(
+ .CLKFX_MULTIPLY(4),
+ .CLKFX_DIVIDE(16),
+ .CLKIN_PERIOD("20 ns")
+ ) vgadcm (
+ .CLKIN (clk),
+ .CLKFB(vga_clk_fb),
+ .CLKFX (vga_clk_unbuffered),
+ .CLK0 (vga_clk_fb)
+ );
+
wire [31:0] vga_pixel_addr_;
wire vga_pixel_r;
assign inAddr = inX_d + (inY_d * 640);
- vram vram(clk, rst, we, inAddr[18:0], vga_pixel_addr_[20:2], inData_d, , mem_out);
+ vram vram(clk, !rst, we, inAddr[18:0], vga_pixel_addr_[20:2], inData_d, , mem_out);
wb_vga wb_vga(
.wb_clk_i(clk),
- .wb_rst_i(!rst),
+ .wb_rst_i(rst),
.fbwb_adr_o(vga_pixel_addr_),
.fbwb_stb_o(vga_pixel_r),
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
`reset
end else begin
- `flush
+ `cleanup
vga_pixel_a <= vga_pixel_r;
- if (!inData_r_ && inData_a) inData_a <= 0;
- if (!inX_r_ && inX_a) inX_a <= 0;
- if (!inY_r_ && inY_a) inY_a <= 0;
- if (inX_r && !inX_a && inY_r && !inY_a && inData_r && !inData_a) begin
+ if (`inX_full && `inY_full && `inData_full) begin
we <= 1;
- inX_a <= 1;
- inY_a <= 1;
- inData_a <= 1;
+ `drain_inX
+ `drain_inY
+ `drain_inData
end else begin
we <= 0;
end
== Test ==============================================================
+#skip
// can't test much here; just make sure it accepts values
#expect 0