import edu.berkeley.fleet.two.*;
import static edu.berkeley.fleet.two.FleetTwoFleet.*;
import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
+import static edu.berkeley.fleet.fpga.verilog.Verilog.PercolatedPort;
public class Fpga extends FleetTwoFleet {
+ public Module top;
+ public FabricElement top_horn;
+ Ship debugShip;
+
+ public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
+ public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
+
public Ship getShip(String type, int ordinal) {
for(Ship s : this)
if (s.getType().equals(type))
- if (ordinal-- < 0)
+ if (--ordinal < 0)
return s;
return null;
}
- public int getWordWidth() { return 37; }
- private static final BitVector SIGNAL_ZERO = new BitVector(1);
- private static final BitVector SIGNAL_ONE = new BitVector(1);
- static {
- SIGNAL_ONE.set(0,true);
- }
-
- public Module top;
- public FabricElement top_horn;
-
- public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
- public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
-
public static void main(String[] s) throws Exception {
- String prefix = s[0];
-
- new FunnelModule().dump(prefix);
- new HornModule().dump(prefix);
-
- new FifoModule(0).dump(prefix);
- new FifoModule(4).dump(prefix);
- new FifoModule(8).dump(prefix);
- new FpgaDock.DockModule(false).dump(prefix);
- new FpgaDock.DockModule(true).dump(prefix);
-
- Module top = new Module("root");
- new Fpga(top).top.dump(prefix);
+ new Fpga(new Module("root")).top.dump(s[0]);
+ PrintWriter pw;
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
+ pw.println("`timescale 1ns / 10ps");
+ pw.close();
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
+ pw.println("`define BRAM_ADDR_WIDTH 14");
+ pw.println("`define BRAM_DATA_WIDTH `WORDWIDTH");
+ pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
+ pw.println("`define BRAM_NAME bram14");
+ pw.println("`include \"bram.inc\"");
+ pw.close();
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v")));
+ pw.println("`define BRAM_ADDR_WIDTH 19");
+ pw.println("`define BRAM_DATA_WIDTH 3");
+ pw.println("`define BRAM_SIZE (640*480)");
+ pw.println("`define BRAM_NAME vram");
+ pw.println("`include \"bram.inc\"");
+ pw.close();
}
+ public Module getVerilogModule() { return top; }
+
public FleetProcess run(Instruction[] instructions) {
try {
return new Client(this, "none", instructions);
} catch (Exception e) { throw new RuntimeException(e); }
}
+ public BitVector getDestAddr(Path path) {
+ return ((FpgaPath)path).toBitVector();
+ }
+
// Setup //////////////////////////////////////////////////////////////////////////////
public Ship createShip(String type, String name) throws IOException {
public Fpga(Module top) throws Exception {
this.top = top;
debugShip = createShip("Debug", "debug");
- createShip("Memory", "memory");
- createShip("Fifo", "fifo1");
- createShip("Fifo", "fifo2");
- createShip("Alu2", "alu2a");
- createShip("Rotator", "rotator");
- //createShip("Alu1", "alu1");
- createShip("Lut3", "lut3");
- createShip("Alu3", "alu3");
-
- Module fifostage = new FifoModule(0);
- Module fifo4 = new FifoModule(4);
- Module fifo8 = new FifoModule(8);
- Module horn = new HornModule();
- Module funnel = new FunnelModule();
- Module outbox = new FpgaDock.DockModule(false);
- Module inbox = new FpgaDock.DockModule(true);
-
- Module.SinkPort debug_in = top.createWirePort("debug_in", WIDTH_PACKET);
+
+ //boolean small = false;
+ boolean small = true;
+
+ createShip("Memory", "memory1");
+
+ if (small) {
+ for(int i=0; i<2; i++)
+ createShip("Fifo", "fifo"+i);
+ for(int i=0; i<2; i++)
+ createShip("Alu", "alu"+i);
+ createShip("Counter", "counter");
+ createShip("CarrySaveAdder", "csa1");
+ createShip("Rotator", "rotator");
+ createShip("Lut3", "lut");
+ } else {
+ createShip("Memory", "memory2");
+ createShip("Memory", "memory3");
+
+ for(int i=0; i<3; i++)
+ createShip("Alu", "alu"+i);
+
+ for(int i=0; i<1; i++)
+ createShip("Fifo", "fifo"+i);
+
+ for(int i=0; i<14; i++)
+ createShip("Counter", "counter"+i);
+
+ /*
+ createShip("CarrySaveAdder", "csa1");
+ createShip("Rotator", "rotator");
+ createShip("Lut3", "lut");
+ */
+ //createShip("DDR2", "ddr2");
+ }
+ createShip("DRAM", "dram");
+ createShip("Video", "video");
+
+ //Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
Module.SourcePort debug_out = null;
for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
if (ship.getType().toLowerCase().equals("debug"))
debug_out = ship.getVerilogModule().getOutputPort("debug_out");
}
+ // for FifoShip
+ new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
+
Module.SourcePort in = top.createInputPort("in", 8);
Module.SinkPort out = top.createOutputPort("out", 8, "");
- Module.Latch temp_in = top.new Latch("temp", WIDTH_PACKET) { public String doReset() { return name+"=0;"; } };
+ Module.Latch temp_in = top.new Latch("temp", WIDTH_PACKET);
Module.Latch count = top.new Latch("count", 8);
Module.Latch count_out = top.new Latch("count_out", 8);
- top.new Event(new Object[] { in, debug_in },
- new Object[] { new SimpleAction(temp_in.getVerilogName()+" = ("+temp_in.getVerilogName()+" << 8) | in;"),
- new SimpleAction("if (count >= 5) begin"+
- " count <= 0; "+
- " `packet_token("+debug_in.getVerilogName()+") <= 0;"+
- " `packet_data("+debug_in.getVerilogName()+") <= "+temp_in.getVerilogName()+";"+
- " `packet_dest("+debug_in.getVerilogName()+") <= `instruction_dest("+temp_in.getVerilogName()+");"+
- " "+debug_in.getVerilogName()+"_r <= 1; "+
- "end else count <= count+1; "),
- in
- });
- top.new Event(new Object[] { out, debug_out },
- new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
- new SimpleAction("if (count_out >= 5) begin "+
- "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+
- " else count_out <= count_out+1; "),
- out });
- ArrayList sources = new ArrayList<FabricElement>();
- ArrayList dests = new ArrayList<FabricElement>();
+ ArrayList inbox_sources = new ArrayList<FabricElement>();
+ ArrayList inbox_dests = new ArrayList<FabricElement>();
+ ArrayList outbox_sources = new ArrayList<FabricElement>();
+ ArrayList outbox_dests = new ArrayList<FabricElement>();
+ ArrayList instruction_dests = new ArrayList<FabricElement>();
+ int numdocks = 0;
for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
if (ship.getType().toLowerCase().equals("debug"))
debug_out = ship.getVerilogModule().getOutputPort("debug_out");
for(Dock port : ship) {
- sources.add(((FpgaDock)port));
- dests.add(port.getInstructionDestination());
- dests.add(port.getDataDestination());
+ if (port.isInputDock()) {
+ inbox_sources.add(((FpgaDock)port));
+ instruction_dests.add(port.getInstructionDestination());
+ inbox_dests.add(port.getDataDestination());
+ } else {
+ outbox_sources.add(((FpgaDock)port));
+ instruction_dests.add(port.getInstructionDestination());
+ outbox_dests.add(port.getDataDestination());
+ }
+ numdocks++;
}
}
+ ArrayList dests = new ArrayList<FabricElement>();
+ ArrayList sources = new ArrayList<FabricElement>();
+ sources.addAll(inbox_sources);
+ sources.addAll(outbox_sources);
+ dests.addAll(inbox_dests);
+ dests.addAll(instruction_dests);
+ dests.addAll(outbox_dests);
top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
FabricElement source = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
- FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(top, debug_in, source.getOutputPort());
+ FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
((FunnelModule.FunnelInstance)source).out = top_funnel;
- //top_horn.addInput(top_funnel, top_funnel.getOutputPort());
top_funnel.addOutput(top_horn, top_horn.getInputPort());
+ Module.SinkPort debug_in = top_funnel.getInputPort("in1");
+
+ top.new Event(new Object[] { in, "count<=7" },
+ new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
+ new AssignAction(count, count.getVerilogName()+"+1"),
+ in
+ });
+ top.new Event(new Object[] { debug_in, "count>7" },
+ new Object[] { new AssignAction(count, "0"),
+ new AssignAction(debug_in, temp_in),
+ debug_in
+ });
+ top.new Event(new Object[] { out, debug_out },
+ new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
+ new ConditionalAction("count_out >= 5", debug_out),
+ new ConditionalAction("count_out >= 5", new AssignAction(count_out, "0")),
+ new ConditionalAction("count_out < 5", new AssignAction(count_out, "count_out+1")),
+ out });
+
}
public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
FabricElement leftPort = mkNode(ports, is_horn, start, (end+start)/2);
FabricElement rightPort = mkNode(ports, is_horn, (end+start)/2, end);
return is_horn
- ? new HornModule.HornInstance(top, leftPort, rightPort)
- : new FunnelModule.FunnelInstance(top, leftPort, rightPort);
+ ? new HornModule.HornInstance(this, top, leftPort, rightPort)
+ : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
}
}
}
- public Module getVerilogModule() { return top; }
-
// Expand //////////////////////////////////////////////////////////////////////////////
FileOutputStream out = new FileOutputStream(outf);
PrintWriter pw = new PrintWriter(out);
- boolean auto = !"debug".equals(filename);
+ boolean debug = "debug".equals(filename);
+
+ pw.println("`define WORDWIDTH "+WIDTH_WORD);
+ pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth);
+ pw.println();
+
+ for(DockDescription dd : sd) {
+ String name = dd.getName();
+ pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
+ pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
+ if (dd.isInputDock()) {
+ pw.println("`define drain_"+name+" "+name+"_a <= 1;");
+ } else {
+ pw.println("`define fill_"+name+" "+name+"_r <= 1;");
+ pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
+ }
+ }
+ if (debug) {
+ String name = "out";
+ pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
+ pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
+ pw.println("`define fill_"+name+" "+name+"_r <= 1;");
+ pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
+ }
- if (auto) {
- pw.println("`include \"macros.v\"");
- pw.println();
+ pw.print("`define reset ");
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
+ else pw.print(bb_name+"_r <= 0; ");
+ }
+ if (debug) {
+ String bb_name = "out";
+ pw.print(bb_name+"_r <= 0; ");
+ }
+ pw.println();
- pw.print("`define reset ");
- for(DockDescription bb : sd) {
- String bb_name = bb.getName();
- if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; ");
- else pw.print(bb_name+"_r <= 0; ");
+ pw.print("`define cleanup ");
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; ");
+ else pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
+ }
+ if (debug) {
+ String bb_name = "out";
+ pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
+ }
+ pw.println();
+
+ // FIXME: this corresponds to something
+ /*
+ pw.print("`define flush_happening (1");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a && "+bb.getName()+"_d["+WIDTH_WORD+"]");
+ pw.println(")");
+ */
+
+ pw.print("`define flush ");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
+ pw.print("if (1");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
+ pw.print(") begin ");
+ if (true) {
+ pw.print("if (1");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
+ pw.print(") begin ");
+ if (true) {
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(bb.getName()+"_f <= 1; ");
+ }
+ pw.print(" end else if (0");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
+ pw.print(") begin ");
+ if (true) {
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
+ }
+ pw.print(" end ");
+ }
+ pw.print(" end ");
+ pw.println();
+
+ pw.println("module " + filename + "( clk, rst ");
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ pw.print(" ");
+ if (bb.isInputDock()) {
+ pw.print(", " + bb_name+"_r_");
+ pw.print(", " + bb_name+"_a_");
+ pw.print(", " + bb_name+"_d");
+ } else {
+ pw.print(", " + bb_name+"_r_");
+ pw.print(", " + bb_name+"_a");
+ pw.print(", " + bb_name+"_d_");
}
pw.println();
+ }
+ if (filename.equals("debug")) {
+ pw.println(" , out_r_");
+ pw.println(" , out_a");
+ pw.println(" , out_d_");
+ }
+ for(PercolatedPort pp : sd.percolatedPorts) {
+ pw.print(" , ");
+ pw.println(pp.name);
+ }
+ if (filename.equals("ddr2")) {
+ pw.println(" , ddr2_addr_");
+ pw.println(" , ddr2_addr_r_");
+ pw.println(" , ddr2_addr_a");
+ pw.println(" , ddr2_isread_");
+ pw.println(" , ddr2_write_data_");
+ pw.println(" , ddr2_write_data_push_");
+ pw.println(" , ddr2_write_data_full");
+ pw.println(" , ddr2_read_data");
+ pw.println(" , ddr2_read_data_pop_");
+ pw.println(" , ddr2_read_data_empty");
+ pw.println(" , ddr2_read_data_latency");
+ }
+ if (filename.equals("video")) {
+ pw.println(" , vga_clk");
+ pw.println(" , vga_psave");
+ pw.println(" , vga_hsync");
+ pw.println(" , vga_vsync");
+ pw.println(" , vga_sync");
+ pw.println(" , vga_blank");
+ pw.println(" , vga_r");
+ pw.println(" , vga_g");
+ pw.println(" , vga_b");
+ pw.println(" , vga_clkout");
+ }
+ pw.println(" );");
+ pw.println();
+ pw.println(" input clk;");
+ pw.println(" input rst;");
+ for(PercolatedPort pp : sd.percolatedPorts) {
+ pw.print(pp.up ? "output" : "input");
+ pw.print(" ");
+ if (pp.width > 1)
+ pw.print("["+(pp.width-1)+":0]");
+ pw.print(" ");
+ pw.print(pp.name);
+ pw.println(";");
+ }
+ if (filename.equals("ddr2")) {
+ pw.println("output [31:0] ddr2_addr_;");
+ pw.println("output ddr2_addr_r_;");
+ pw.println("input ddr2_addr_a;");
+ pw.println("output ddr2_isread_;");
+ pw.println("output [63:0] ddr2_write_data_;");
+ pw.println("output ddr2_write_data_push_;");
+ pw.println("input ddr2_write_data_full;");
+ pw.println("input [63:0] ddr2_read_data;");
+ pw.println("output ddr2_read_data_pop_;");
+ pw.println("input ddr2_read_data_empty;");
+ pw.println("input [1:0] ddr2_read_data_latency;");
+ }
+ if (filename.equals("video")) {
+ pw.println("input vga_clk;");
+ pw.println("output vga_psave;");
+ pw.println("output vga_hsync;");
+ pw.println("output vga_vsync;");
+ pw.println("output vga_sync;");
+ pw.println("output vga_blank;");
+ pw.println("output [7:0] vga_r;");
+ pw.println("output [7:0] vga_g;");
+ pw.println("output [7:0] vga_b;");
+ pw.println("output vga_clkout;");
+ }
- pw.println("module " + filename + "( clk, rst ");
- for(DockDescription bb : sd) {
- String bb_name = bb.getName();
- pw.print(" ");
- if (bb.isInputDock()) {
- pw.print(", " + bb_name+"_r");
- pw.print(", " + bb_name+"_a_");
- pw.print(", " + bb_name+"_d");
- } else {
- pw.print(", " + bb_name+"_r_");
- pw.print(", " + bb_name+"_a");
- pw.print(", " + bb_name+"_d_");
- }
- pw.println();
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInputDock()) {
+ pw.println(" input ["+WIDTH_WORD+":0] "+bb_name+"_d;");
+ pw.println(" input "+bb_name+"_r_;");
+ pw.println(" wire "+bb_name+"_r;");
+ pw.println(" assign "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+WIDTH_WORD+"];");
+ pw.println(" output "+bb_name+"_a_;");
+ pw.println(" reg "+bb_name+"_a;");
+ pw.println(" initial "+bb_name+"_a = 0;");
+ pw.println(" reg "+bb_name+"_f;");
+ pw.println(" initial "+bb_name+"_f = 0;");
+ pw.println(" assign "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
+ } else {
+ pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
+ pw.println(" input "+bb_name+"_a;");
+ pw.println(" output "+bb_name+"_r_;");
+ pw.println(" reg "+bb_name+"_r;");
+ pw.println(" initial "+bb_name+"_r = 0;");
+ pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
}
- pw.println(" );");
pw.println();
- pw.println(" input clk;");
- pw.println(" input rst;");
- for(DockDescription bb : sd) {
- String bb_name = bb.getName();
- pw.print(" ");
- if (bb.isInputDock()) {
- pw.println("`input(" +
- bb_name+"_r, "+
- bb_name+"_a, "+
- bb_name+"_a_, "+
- "[("+WIDTH_WORD+"-1):0],"+
- bb_name+"_d)"
- );
- } else {
- pw.println("`output(" +
- bb_name+"_r, "+
- bb_name+"_r_, "+
- bb_name+"_a, "+
- "[("+WIDTH_WORD+"-1):0],"+
- bb_name+"_d_)"
- );
- if (!bb_name.equals("out") || !"memory".equals(filename))
- pw.println("`defreg(" +
- bb_name+"_d_, "+
- "[("+WIDTH_WORD+"-1):0],"+
- bb_name+"_d)"
- );
- }
- pw.println();
- }
+ }
+ if (filename.equals("debug")) {
+ String bb_name = "out";
+ pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
+ pw.println(" input "+bb_name+"_a;");
+ pw.println(" output "+bb_name+"_r_;");
+ pw.println(" reg "+bb_name+"_r;");
+ pw.println(" initial "+bb_name+"_r = 0;");
+ pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
}
- pw.println(sd.getSection("fpga"));
+ if (filename.equals("fifo")) {
+ pw.println(" wire in_a__;");
+ pw.println(" wire out_r__;");
+ pw.println(" fifo8x37 fifo8x37(clk, rst,");
+ pw.println(" in_r, in_a__, in_d,");
+ pw.println(" out_r__, out_a, out_d_);");
+ pw.println(" always @(posedge clk) begin");
+ pw.println(" if (!rst) begin");
+ pw.println(" `reset");
+ pw.println(" end else begin");
+ pw.println(" `flush");
+ pw.println(" out_r <= out_r__;");
+ pw.println(" in_a <= in_a__;");
+ pw.println(" end");
+ pw.println(" end");
+ } else {
+ pw.println(sd.getSection("fpga"));
+ }
- if (auto)
- pw.println("endmodule");
+ pw.println("endmodule");
pw.flush();
pw.close();
} catch (Exception e) { throw new RuntimeException(e); }
}
-
- Ship debugShip;
-
-
- public long getDestAddr(Path path) {
- return ((FpgaPath)path).toLong();
- }
- public Path getPathByAddr(Dock source, long dest) {
- for(Ship ship : Fpga.this)
- for(Dock bb : ship) {
- for(Destination d : new Destination[] { bb.getInstructionDestination(), bb.getDataDestination() }) {
- for(BitVector signal : new BitVector[] { SIGNAL_ZERO, SIGNAL_ONE }) {
- FpgaPath p = (FpgaPath)source.getPath(d, signal);
- if (p.toLong() == dest) return p;
- }
- }
- }
- return null;
- }
- public Dock getBoxByInstAddr(long dest) {
- for(Ship ship : Fpga.this)
- for(Dock bb : ship)
- if (((FpgaDestination)((FpgaDock)bb).getInstructionDestination()).getAddr() == dest)
- return bb;
- return null;
- }
-
}
projects / fleet.git / blobdiff