add rst wire (but do not do anything with it)

[fleet.git] / src / edu / berkeley / fleet / fpga / Generator.java

diff --git a/src/edu/berkeley/fleet/fpga/Generator.java b/src/edu/berkeley/fleet/fpga/Generator.java
index e0882f7..e0f9c6c 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Generator.java
+++ b/src/edu/berkeley/fleet/fpga/Generator.java
@@ -214,7 +214,7 @@ public class Generator {
                 instantiatedModules.add(this);
             }
             public void dump(PrintWriter pw) {
-                pw.println("  " + module.getName() + " " + getName() + "(clk");
+                pw.println("  " + module.getName() + " " + getName() + "(clk, rst ");
                 for(String s : module.portorder)
                     pw.println(", " + getPort(s).getSimpleInterface());
                 pw.println("   );");
@@ -327,7 +327,7 @@ public class Generator {
 
         public void dump(PrintWriter pw, boolean fix) {
             pw.println("`include \"macros.v\"");
-            pw.println("module "+name+"(clk");
+            pw.println("module "+name+"(clk, rst ");
             for(String name : portorder) {
                 Port p = ports.get(name);
                 pw.println("    , " + p.getInterface());
@@ -335,6 +335,7 @@ public class Generator {
             pw.println("   );");
             pw.println();
             pw.println("    input clk;");
+            pw.println("    input rst;");
             for(String name : ports.keySet()) {
                 Port p = ports.get(name);
                 pw.println("    " + p.getDeclaration());