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+// This copyright and support notice must be retained as part
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//*****************************************************************************
// ____ ____
// / /\/ /
// \ \ \/ Version: 2.3
// \ \ Application: MIG
// / / Filename: ddr2_infrastructure.v
-// /___/ /\ Date Last Modified: $Date: 2008/07/29 15:24:03 $
+// /___/ /\ Date Last Modified: $Date: 2008/05/08 15:20:47 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
-// Clock generation/distribution and reset synchronization
+// Clock distribution and reset synchronization
//Reference:
//Revision History:
-// Rev 1.1 - Parameter CLK_TYPE added and logic for DIFFERENTIAL and
-// SINGLE_ENDED added. PK. 20/6/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_infrastructure #
(
- // Following parameters are for 72-bit RDIMM design (for ML561 Reference
- // board design). Actual values may be different. Actual parameters values
- // are passed from design top module ddr2_sdram module. Please refer to
- // the ddr2_sdram module for actual values.
- parameter CLK_PERIOD = 3000,
- parameter CLK_TYPE = "DIFFERENTIAL",
- parameter DLL_FREQ_MODE = "HIGH",
parameter RST_ACT_LOW = 1
)
(
- input sys_clk_p,
- input sys_clk_n,
- input sys_clk,
- input clk200_p,
- input clk200_n,
- input idly_clk_200,
- output clk0,
- output clk90,
- output clk200,
- output clkdiv0,
+ input clk0,
+ input clk90,
+ input clk200,
+ input clkdiv0,
+ input dcm_lock,
input sys_rst_n,
input idelay_ctrl_rdy,
output rst0,
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
localparam RST_SYNC_NUM = 25;
- localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
- wire clk0_bufg;
- wire clk90_bufg;
- wire clk200_bufg;
- wire clk200_ibufg;
- wire clkdiv0_bufg;
- wire dcm_clk0;
- wire dcm_clk90;
- wire dcm_clkdiv0;
- wire dcm_lock;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */;
assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
- assign clk0 = clk0_bufg;
- assign clk90 = clk90_bufg;
- assign clk200 = clk200_bufg;
- assign clkdiv0 = clkdiv0_bufg;
-
- generate
- if(CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST
- //***************************************************************************
- // Differential input clock input buffers
- //***************************************************************************
-
- IBUFGDS_LVPECL_25 SYS_CLK_INST
- (
- .I (sys_clk_p),
- .IB (sys_clk_n),
- .O (sys_clk_ibufg)
- );
-
- IBUFGDS_LVPECL_25 IDLY_CLK_INST
- (
- .I (clk200_p),
- .IB (clk200_n),
- .O (clk200_ibufg)
- );
-
- end else if(CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST
- //**************************************************************************
- // Single ended input clock input buffers
- //**************************************************************************
-
- // AM -- edits: changed IBUFG to BUF
-
- BUF SYS_CLK_INST
- (
- .I (sys_clk),
- .O (sys_clk_ibufg)
- );
-
- BUF IDLY_CLK_INST
- (
- .I (idly_clk_200),
- .O (clk200_ibufg)
- );
-
- end
- endgenerate
-
- BUFG CLK_200_BUFG
- (
- .O (clk200_bufg),
- .I (clk200_ibufg)
- );
-
- //***************************************************************************
- // Global clock generation and distribution
- //***************************************************************************
-
- DCM_BASE #
- (
- .CLKIN_PERIOD (CLK_PERIOD_NS),
- .CLKDV_DIVIDE (2.0),
- .DLL_FREQUENCY_MODE (DLL_FREQ_MODE),
- .DUTY_CYCLE_CORRECTION ("TRUE"),
- .FACTORY_JF (16'hF0F0)
- )
- u_dcm_base
- (
- .CLK0 (dcm_clk0),
- .CLK180 (),
- .CLK270 (),
- .CLK2X (),
- .CLK2X180 (),
- .CLK90 (dcm_clk90),
- .CLKDV (dcm_clkdiv0),
- .CLKFX (),
- .CLKFX180 (),
- .LOCKED (dcm_lock),
- .CLKFB (clk0_bufg),
- .CLKIN (sys_clk_ibufg),
- .RST (sys_rst)
- );
-
- BUFG U_BUFG_CLK0
- (
- .O (clk0_bufg),
- .I (dcm_clk0)
- );
-
- BUFG U_BUFG_CLK90
- (
- .O (clk90_bufg),
- .I (dcm_clk90)
- );
-
- BUFG U_BUFG_CLKDIV0
- (
- .O (clkdiv0_bufg),
- .I (dcm_clkdiv0)
- );
//***************************************************************************
assign rst_tmp = sys_rst | ~dcm_lock | ~idelay_ctrl_rdy;
// synthesis attribute max_fanout of rst0_sync_r is 10
- always @(posedge clk0_bufg or posedge rst_tmp)
+ always @(posedge clk0 or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
rst0_sync_r <= rst0_sync_r << 1;
// synthesis attribute max_fanout of rstdiv0_sync_r is 10
- always @(posedge clkdiv0_bufg or posedge rst_tmp)
+ always @(posedge clkdiv0 or posedge rst_tmp)
if (rst_tmp)
rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}};
else
rstdiv0_sync_r <= rstdiv0_sync_r << 1;
// synthesis attribute max_fanout of rst90_sync_r is 10
- always @(posedge clk90_bufg or posedge rst_tmp)
+ always @(posedge clk90 or posedge rst_tmp)
if (rst_tmp)
rst90_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg
// synthesis attribute max_fanout of rst200_sync_r is 10
- always @(posedge clk200_bufg or negedge dcm_lock)
+ always @(posedge clk200 or negedge dcm_lock)
if (!dcm_lock)
rst200_sync_r <= {RST_SYNC_NUM{1'b1}};
else
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