DDR2 ship: works on ML509

[fleet.git] / src / edu / berkeley / fleet / fpga / ddr2 / ddr2_phy_calib.v

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v
index 349dd7a..76a0751 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_calib.v
@@ -1232,8 +1232,8 @@ module ddr2_phy_calib #
          .D   (cal2_rd_data_sel[rd_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /* */
-           /*  */;
+         ) /* synthesis syn_preserve = 1 */
+           /* synthesis syn_replicate = 0 */;
     end
   endgenerate
 
@@ -1505,8 +1505,8 @@ module ddr2_phy_calib #
          .D   (calib_rden_srl_a[cal_rden_ff_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /*  */
-           /*  */;
+         ) /* synthesis syn_preserve = 1 */
+           /* synthesis syn_replicate = 0 */;
     end
   endgenerate
 
@@ -1528,7 +1528,7 @@ module ddr2_phy_calib #
          .D   (calib_rden_srl_out),
          .R   (1'b0),
          .S   (1'b0)
-     ) /*  */;
+     ) /* synthesis syn_preserve = 1 */;
 
   // convert to CLKDIV domain. Two version are generated because we need
   // to be able to tell exactly which fast (clk) clock cycle the read
@@ -1560,8 +1560,8 @@ module ddr2_phy_calib #
          .D   (rden_dly[rden_ff_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /*  */
-           /*  */;
+         ) /* synthesis syn_preserve = 1 */
+           /* synthesis syn_replicate = 0 */;
     end
   endgenerate
 
@@ -1590,7 +1590,7 @@ module ddr2_phy_calib #
          .D   (rden_srl_out[rden_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /*  */;
+         ) /* synthesis syn_preserve = 1 */;
     end
   endgenerate
 
@@ -2004,8 +2004,8 @@ module ddr2_phy_calib #
          .D   (gate_dly[gate_ff_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /*  */
-           /*  */;
+         ) /* synthesis syn_preserve = 1 */
+           /* synthesis syn_replicate = 0 */;
     end
   endgenerate
 
@@ -2044,7 +2044,7 @@ module ddr2_phy_calib #
          .D   (gate_srl_out[gate_i]),
          .R   (1'b0),
          .S   (1'b0)
-           ) /*  */;
+           ) /* synthesis syn_preserve = 1 */;
       end else begin: gen_gate_base_dly_le3
         assign gate_srl_out_r[gate_i] = gate_srl_out[gate_i];
       end
@@ -2057,8 +2057,8 @@ module ddr2_phy_calib #
          .D   (gate_srl_out_r[gate_i]),
          .R   (1'b0),
          .S   (1'b0)
-         ) /*  */
-           /*  */;
+         ) /* synthesis syn_preserve = 1 */
+           /* synthesis syn_replicate = 0 */;
     end
   endgenerate