DDR2 ship: works on ML509

[fleet.git] / src / edu / berkeley / fleet / fpga / ddr2 / ddr2_phy_ctl_io.v

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v
index d0e5de1..625a5dc 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_ctl_io.v
@@ -179,7 +179,7 @@ module ddr2_phy_ctl_io #
      .CLR (1'b0),
      .D   (ras_n_mux),
      .PRE (rst0)
-     ) /*  */;
+     ) /* synthesis syn_useioff = 1 */;
 
   // CAS: = 1 at reset
   (* IOB = "TRUE" *) FDCPE u_ff_cas_n
@@ -190,7 +190,7 @@ module ddr2_phy_ctl_io #
      .CLR (1'b0),
      .D   (cas_n_mux),
      .PRE (rst0)
-     ) /*  */;
+     ) /* synthesis syn_useioff = 1 */;
 
   // WE: = 1 at reset
   (* IOB = "TRUE" *) FDCPE u_ff_we_n
@@ -201,7 +201,7 @@ module ddr2_phy_ctl_io #
      .CLR (1'b0),
      .D   (we_n_mux),
      .PRE (rst0)
-     ) /*  */;
+     ) /* synthesis syn_useioff = 1 */;
 
   // CKE: = 0 at reset
   genvar cke_i;
@@ -215,7 +215,7 @@ module ddr2_phy_ctl_io #
          .CLR (rst0),
          .D   (phy_init_cke[cke_i]),
          .PRE (1'b0)
-         ) /*  */;
+         ) /* synthesis syn_useioff = 1 */;
     end
   endgenerate
 
@@ -238,7 +238,7 @@ module ddr2_phy_ctl_io #
             .CLR (1'b0),
             .D   (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
             .PRE (rst0)
-            ) /*  */;
+            ) /* synthesis syn_useioff = 1 */;
       end else begin // if (TWO_T_TIME_EN)
          (* IOB = "TRUE" *) FDCPE u_ff_cs_n
            (
@@ -248,7 +248,7 @@ module ddr2_phy_ctl_io #
             .CLR (1'b0),
             .D   (cs_n_mux[(cs_i*CS_NUM)/CS_WIDTH]),
             .PRE (rst0)
-            ) /*  */;
+            ) /* synthesis syn_useioff = 1 */;
       end // else: !if(TWO_T_TIME_EN)
     end
   endgenerate
@@ -265,7 +265,7 @@ module ddr2_phy_ctl_io #
          .CLR (1'b0),
          .D   (addr_mux[addr_i]),
          .PRE (1'b0)
-         ) /*  */;
+         ) /* synthesis syn_useioff = 1 */;
     end
   endgenerate
 
@@ -281,7 +281,7 @@ module ddr2_phy_ctl_io #
          .CLR (1'b0),
          .D   (ba_mux[ba_i]),
          .PRE (1'b0)
-         ) /*  */;
+         ) /* synthesis syn_useioff = 1 */;
     end
   endgenerate
 
@@ -298,7 +298,7 @@ module ddr2_phy_ctl_io #
            .CLR (rst0),
           .D   (odt[(odt_i*CS_NUM)/ODT_WIDTH]),
            .PRE (1'b0)
-           ) /*  */;
+           ) /* synthesis syn_useioff = 1 */;
       end
     end
   endgenerate