DDR2 ship: works on ML509

[fleet.git] / src / edu / berkeley / fleet / fpga / ddr2 / ddr2_phy_dq_iob.v

diff --git a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v
index 7a8ff90..854079a 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v
+++ b/src/edu/berkeley/fleet/fpga/ddr2/ddr2_phy_dq_iob.v
@@ -360,8 +360,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -372,8 +372,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       // Stage 3 falling -> rising edge translation
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -385,8 +385,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/* */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -397,8 +397,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/* */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       //*********************************************************
       // Slice #2 (posedge CLK): Used for:
@@ -415,8 +415,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/* */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -428,8 +428,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
     end else if ((DQ_MS == 0) && (DQ_COL == 0)) begin: gen_stg2_0s
 
@@ -462,8 +462,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -474,8 +474,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -487,8 +487,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -499,8 +499,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
        AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -512,8 +512,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
        AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -524,8 +524,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_0s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
     end else if ((DQ_MS == 1) && (DQ_COL == 1))  begin: gen_stg2_1m
 
@@ -558,8 +558,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -570,8 +570,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -583,8 +583,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -595,8 +595,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -608,8 +608,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -620,8 +620,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
     end else if ((DQ_MS == 0) && (DQ_COL == 1)) begin: gen_stg2_1s
 
@@ -654,8 +654,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -666,8 +666,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -679,8 +679,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -691,8 +691,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -704,8 +704,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -716,8 +716,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_1s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
     end else if ((DQ_MS == 1) && (DQ_COL == 2)) begin: gen_stg2_2m
 
@@ -750,8 +750,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -762,8 +762,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -775,8 +775,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X0Y0", BEL = "BFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -787,8 +787,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -800,8 +800,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X1Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -812,8 +812,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2m),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
     end else if ((DQ_MS == 0) && (DQ_COL == 2)) begin: gen_stg2_2s
 
@@ -846,8 +846,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "DFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg2a_rise
@@ -858,8 +858,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_fall
@@ -870,8 +870,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_fall),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X2Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE u_ff_stg3b_rise
@@ -882,8 +882,8 @@ module ddr2_phy_dq_iob #
      .D   (stg2b_out_rise),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "AFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
@@ -895,8 +895,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_fall_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
       (* HU_SET = "stg2_capture", RLOC = "X3Y0", BEL = "CFF",
          AREA_GROUP = "DDR_CAPTURE_FFS" *)
       FDRSE_1 u_ff_stg2b_rise
@@ -907,8 +907,8 @@ module ddr2_phy_dq_iob #
      .D   (stg1_out_rise_2s),
          .R   (1'b0),
          .S   (1'b0)
-         )/*  */
-          /*  */;
+         )/* synthesis syn_preserve = 1 */
+          /* synthesis syn_replicate = 0 */;
 
     end
   endgenerate