-Net DDR2_CAS_B LOC=E31; Net DDR2_CAS_B IOSTANDARD="SSTL18_II";
-
-Net DDR2_CKE<1> LOC=U30; Net DDR2_CKE<1> IOSTANDARD="SSTL18_II";
-Net DDR2_CKE<0> LOC=T28; Net DDR2_CKE<0> IOSTANDARD="SSTL18_II";
-
-Net DDR2_RAS_B LOC=H30; Net DDR2_RAS_B IOSTANDARD="SSTL18_II";
-
-Net DDR2_WE_B LOC=K29; Net DDR2_WE_B IOSTANDARD="SSTL18_II";
-
-Net DDR2_ODT<1> LOC=F30; Net DDR2_ODT<1> IOSTANDARD="SSTL18_II";
-Net DDR2_ODT<0> LOC=F31; Net DDR2_ODT<0> IOSTANDARD="SSTL18_II";
-
-Net DDR2_CS0_B<1> LOC=J29; Net DDR2_CS0_B<1> IOSTANDARD="SSTL18_II";
-Net DDR2_CS0_B<0> LOC=L29; Net DDR2_CS0_B<0> IOSTANDARD="SSTL18_II";
-
-Net DDR2_CLK_N<1> LOC=F28; Net DDR2_CLK_N<1> IOSTANDARD="DIFF_SSTL18_II";
-Net DDR2_CLK_N<0> LOC=AJ29; Net DDR2_CLK_N<0> IOSTANDARD="DIFF_SSTL18_II";
-
-Net DDR2_CLK_P<1> LOC=E28; Net DDR2_CLK_P<1> IOSTANDARD="DIFF_SSTL18_II";
-Net DDR2_CLK_P<0> LOC=AK29; Net DDR2_CLK_P<0> IOSTANDARD="DIFF_SSTL18_II";
-
-Net DDR2_A<13> LOC=H29; Net DDR2_A<13> IOSTANDARD="SSTL18_II";
-Net DDR2_A<12> LOC=T31; Net DDR2_A<12> IOSTANDARD="SSTL18_II";
-Net DDR2_A<11> LOC=R29; Net DDR2_A<11> IOSTANDARD="SSTL18_II";
-Net DDR2_A<10> LOC=J31; Net DDR2_A<10> IOSTANDARD="SSTL18_II";
-Net DDR2_A<9> LOC=R28; Net DDR2_A<9> IOSTANDARD="SSTL18_II";
-Net DDR2_A<8> LOC=M31; Net DDR2_A<8> IOSTANDARD="SSTL18_II";
-Net DDR2_A<7> LOC=P30; Net DDR2_A<7> IOSTANDARD="SSTL18_II";
-Net DDR2_A<6> LOC=P31; Net DDR2_A<6> IOSTANDARD="SSTL18_II";
-Net DDR2_A<5> LOC=L31; Net DDR2_A<5> IOSTANDARD="SSTL18_II";
-Net DDR2_A<4> LOC=K31; Net DDR2_A<4> IOSTANDARD="SSTL18_II";
-Net DDR2_A<3> LOC=P29; Net DDR2_A<3> IOSTANDARD="SSTL18_II";
-Net DDR2_A<2> LOC=N29; Net DDR2_A<2> IOSTANDARD="SSTL18_II";
-Net DDR2_A<1> LOC=M30; Net DDR2_A<1> IOSTANDARD="SSTL18_II";
-Net DDR2_A<0> LOC=L30; Net DDR2_A<0> IOSTANDARD="SSTL18_II";
-
-Net DDR2_BA<2> LOC=R31; Net DDR2_BA<2> IOSTANDARD="SSTL18_II";
-Net DDR2_BA<1> LOC=J30; Net DDR2_BA<1> IOSTANDARD="SSTL18_II";
-Net DDR2_BA<0> LOC=G31; Net DDR2_BA<0> IOSTANDARD="SSTL18_II";
-
-Net DDR2_DQ<63> LOC=L24; Net DDR2_DQ<63> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<62> LOC=L25; Net DDR2_DQ<62> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<61> LOC=M25; Net DDR2_DQ<61> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<60> LOC=J27; Net DDR2_DQ<60> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<59> LOC=L26; Net DDR2_DQ<59> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<58> LOC=J24; Net DDR2_DQ<58> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<57> LOC=M26; Net DDR2_DQ<57> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<56> LOC=G25; Net DDR2_DQ<56> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<55> LOC=G26; Net DDR2_DQ<55> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<54> LOC=H24; Net DDR2_DQ<54> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<53> LOC=K28; Net DDR2_DQ<53> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<52> LOC=K27; Net DDR2_DQ<52> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<51> LOC=H25; Net DDR2_DQ<51> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<50> LOC=F25; Net DDR2_DQ<50> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<49> LOC=L28; Net DDR2_DQ<49> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<48> LOC=M28; Net DDR2_DQ<48> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<47> LOC=N28; Net DDR2_DQ<47> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<46> LOC=P27; Net DDR2_DQ<46> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<45> LOC=N25; Net DDR2_DQ<45> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<44> LOC=T24; Net DDR2_DQ<44> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<43> LOC=P26; Net DDR2_DQ<43> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<42> LOC=N24; Net DDR2_DQ<42> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<41> LOC=P25; Net DDR2_DQ<41> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<40> LOC=R24; Net DDR2_DQ<40> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<39> LOC=V24; Net DDR2_DQ<39> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<38> LOC=W26; Net DDR2_DQ<38> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<37> LOC=W25; Net DDR2_DQ<37> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<36> LOC=V28; Net DDR2_DQ<36> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<35> LOC=W24; Net DDR2_DQ<35> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<34> LOC=Y26; Net DDR2_DQ<34> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<33> LOC=Y27; Net DDR2_DQ<33> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<32> LOC=V29; Net DDR2_DQ<32> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<31> LOC=W27; Net DDR2_DQ<31> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<30> LOC=V27; Net DDR2_DQ<30> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<29> LOC=W29; Net DDR2_DQ<29> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<28> LOC=AC30; Net DDR2_DQ<28> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<27> LOC=V30; Net DDR2_DQ<27> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<26> LOC=W31; Net DDR2_DQ<26> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<25> LOC=AB30; Net DDR2_DQ<25> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<24> LOC=AC29; Net DDR2_DQ<24> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<23> LOC=AA25; Net DDR2_DQ<23> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<22> LOC=AB27; Net DDR2_DQ<22> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<21> LOC=AA24; Net DDR2_DQ<21> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<20> LOC=AB26; Net DDR2_DQ<20> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<19> LOC=AA26; Net DDR2_DQ<19> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<18> LOC=AC27; Net DDR2_DQ<18> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<17> LOC=AB25; Net DDR2_DQ<17> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<16> LOC=AC28; Net DDR2_DQ<16> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<15> LOC=AB28; Net DDR2_DQ<15> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<14> LOC=AG28; Net DDR2_DQ<14> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<13> LOC=AJ26; Net DDR2_DQ<13> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<12> LOC=AG25; Net DDR2_DQ<12> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<11> LOC=AA28; Net DDR2_DQ<11> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<10> LOC=AH28; Net DDR2_DQ<10> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<9> LOC=AF28; Net DDR2_DQ<9> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<8> LOC=AH27; Net DDR2_DQ<8> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<7> LOC=AE29; Net DDR2_DQ<7> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<6> LOC=AD29; Net DDR2_DQ<6> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<5> LOC=AF29; Net DDR2_DQ<5> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<4> LOC=AJ30; Net DDR2_DQ<4> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<3> LOC=AD30; Net DDR2_DQ<3> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<2> LOC=AF31; Net DDR2_DQ<2> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<1> LOC=AK31; Net DDR2_DQ<1> IOSTANDARD="SSTL18_II_DCI";
-Net DDR2_DQ<0> LOC=AF30; Net DDR2_DQ<0> IOSTANDARD="SSTL18_II_DCI";
-
-Net DDR2_DM<7> LOC=J25; Net DDR2_DM<7> IOSTANDARD="SSTL18_II";
-Net DDR2_DM<6> LOC=F26; Net DDR2_DM<6> IOSTANDARD="SSTL18_II";
-Net DDR2_DM<5> LOC=P24; Net DDR2_DM<5> IOSTANDARD="SSTL18_II";
-Net DDR2_DM<4> LOC=V25; Net DDR2_DM<4> IOSTANDARD="SSTL18_II";
-Net DDR2_DM<3> LOC=Y31; Net DDR2_DM<3> IOSTANDARD="SSTL18_II";
-Net DDR2_DM<2> LOC=Y24; Net DDR2_DM<2> IOSTANDARD="SSTL18_II";
-Net DDR2_DM<1> LOC=AE28; Net DDR2_DM<1> IOSTANDARD="SSTL18_II";
-Net DDR2_DM<0> LOC=AJ31; Net DDR2_DM<0> IOSTANDARD="SSTL18_II";
-
-Net DDR2_DQS_N<7> LOC=H27; Net DDR2_DQS_N<7> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_N<6> LOC=G28; Net DDR2_DQS_N<6> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_N<5> LOC=E27; Net DDR2_DQS_N<5> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_N<4> LOC=Y29; Net DDR2_DQS_N<4> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_N<3> LOC=AA31; Net DDR2_DQS_N<3> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_N<2> LOC=AJ27; Net DDR2_DQS_N<2> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_N<1> LOC=AK27; Net DDR2_DQS_N<1> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_N<0> LOC=AA30; Net DDR2_DQS_N<0> IOSTANDARD="DIFF_SSTL18_II_DCI";
-
-Net DDR2_DQS_P<7> LOC=G27; Net DDR2_DQS_P<7> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_P<6> LOC=H28; Net DDR2_DQS_P<6> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_P<5> LOC=E26; Net DDR2_DQS_P<5> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_P<4> LOC=Y28; Net DDR2_DQS_P<4> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_P<3> LOC=AB31; Net DDR2_DQS_P<3> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_P<2> LOC=AK26; Net DDR2_DQS_P<2> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_P<1> LOC=AK28; Net DDR2_DQS_P<1> IOSTANDARD="DIFF_SSTL18_II_DCI";
-Net DDR2_DQS_P<0> LOC=AA29; Net DDR2_DQS_P<0> IOSTANDARD="DIFF_SSTL18_II_DCI";
-
-Net I2C_DDR2_SCL LOC=E29;
-
-Net I2C_DDR2_SDA LOC=F29;
-
-Net CLKBUF_Q1_N LOC=J19;
-#Net CLKBUF_Q1_N PERIOD="200 Mhz";
-Net CLKBUF_Q1_P LOC=K18;
-#Net CLKBUF_Q1_P PERIOD="200 Mhz";
-
-
## Clock, Reset ##############################################################################
Net clk_pin LOC=AH17;
Net uart_out TIG;
Net uart_out PULLUP;
+## DVI ##############################################################################
+
+NET dvi_d0 LOC="AB8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d1 LOC="AC8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d2 LOC="AN12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d3 LOC="AP12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d4 LOC="AA9"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d5 LOC="AA8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d6 LOC="AM13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d7 LOC="AN13"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d8 LOC="AA10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d9 LOC="AB10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d10 LOC="AP14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_d11 LOC="AN14"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_de LOC="AE8"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_h LOC="AM12"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_reset_b LOC="AK6"; # Bank 18, Vcco=3.3V, No DCI
+NET dvi_v LOC="AM11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_xclk_n LOC="AL10"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET dvi_xclk_p LOC="AL11"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
+
+#NET dvi_gpio1 LOC="N30" | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
+#NET dvi_iic_scl LOC="U27" | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
+#NET dvi_iic_sda LOC="T29" | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
+
+NET gpio_led_c LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI
+NET gpio_led_e LOC="AK7"; # Bank 18, Vcco=3.3V, No DCI
+NET gpio_led_n LOC="U8"; # Bank 18, Vcco=3.3V, No DCI
+NET gpio_led_s LOC="V8"; # Bank 18, Vcco=3.3V, No DCI
+NET gpio_led_w LOC="AJ7"; # Bank 18, Vcco=3.3V, No DCI
+NET gpio_led_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_3 LOC="AD26" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET gpio_led_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI
+NET gpio_led_5 LOC="AD25" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+
+
## VGA ##############################################################################
#net "vga_hsync" loc = f9;
#net "vga_*" iostandard = lvcmos33;
#
-### DRAM ##############################################################################
-
-NET "clk_pin" TNM="SYS_CLK";
-#NET "*/*/clkgen/write_clk_u" TNM="WRITE_CLK";
-#NET "*/*/clkgen/write_clk90_u" TNM="WRITE_CLK";
-#NET "*/*/clkgen/read_clk_u" TNM="READ_CLK";
-#TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG;
-#TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG;
-#TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG;
-#TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG;
-#TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG;
-#TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG;
-
-
-##==============================================================================
-## File: $URL: svn+ssh://repositorypub@repository.eecs.berkeley.edu/public/Projects/GateLib/branches/dev/Firmware/DRAM/Hardware/DDR2SDRAM/Constraints/DDR2SDRAM_ML505_110.ucf $
-## Version: $Revision: 16601 $
-## Author: Greg Gibeling (http://www.eecs.berkeley.edu/~gdgib/)
-## Copyright: Copyright 2005-2008 UC Berkeley
-##==============================================================================
-
-##==============================================================================
-## Section: License
-##==============================================================================
-## Copyright (c) 2005-2008, Regents of the University of California
-## All rights reserved.
+##############################################################################
+##############################################################################
+##############################################################################
+# DDR2
+
+############################################################################
+##
+## Xilinx, Inc. 2006 www.xilinx.com
+## ÐÇÆÚÒ» ¾ÅÔ 22 11:53:57 2008
+## Generated by MIG Version 2.3
+##
+############################################################################
+## File name : ddr2_sdram.ucf
+##
+## Details : Constraints file
+## FPGA family: virtex5
+## FPGA: xc5vlx110t-ff1136
+## Speedgrade: -1
+## Design Entry: VERILOG
+## Frequency: 266.66 MHz
+## Design: with Test bench
+## DCM Used: Enable
+## Two Bytes per Bank:Disable
+## No.Of Controllers: 1
##
-## Redistribution and use in source and binary forms, with or without modification,
-## are permitted provided that the following conditions are met:
-##
-## - Redistributions of source code must retain the above copyright notice,
-## this list of conditions and the following disclaimer.
-## - Redistributions in binary form must reproduce the above copyright
-## notice, this list of conditions and the following disclaimer
-## in the documentation and/or other materials provided with the
-## distribution.
-## - Neither the name of the University of California, Berkeley nor the
-## names of its contributors may be used to endorse or promote
-## products derived from this software without specific prior
-## written permission.
-##
-## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-## WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-## ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-## (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-## ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-## (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##==============================================================================
-
-##==============================================================================
-## Xilinx, Inc. 2006 www.xilinx.com
-## Mon Jul 7 12:05:40 2008
-## Generated by MIG Version 2.2
-##==============================================================================
-## File name: ddr2_sdram.ucf
-## Details: Constraints file
-## FPGA family: virtex5
-## FPGA: xc5vlx110t-ff1136
-## Speedgrade: -1
-## Design Entry: VERILOG
-## Frequency: 266.66 MHz
-## Design: without Test bench
-## DCM Used: Disable
-## Two Bytes per Bank: Disable
-## Compatible FPGA's: xc5vlx85t-ff1136,xc5vlx50t-ff1136,xc5vlx155t-ff1136,xc5vfx70t-ff1136,xc5vfx100t-ff1136,xc5vsx50t-ff1136,xc5vsx95t-ff1136
-## No.Of Controllers: 1
-##==============================================================================
-
-##------------------------------------------------------------------------------
-## Section: Pin Constraints (use FPGA_TOP instead)
-##------------------------------------------------------------------------------
-#NET "ddr2_dq[*]" IOSTANDARD = SSTL18_II_DCI;
-#NET "ddr2_a[*]" IOSTANDARD = SSTL18_II;
-#NET "ddr2_ba[*]" IOSTANDARD = SSTL18_II;
-#NET "ddr2_ras_n" IOSTANDARD = SSTL18_II;
-#NET "ddr2_cas_n" IOSTANDARD = SSTL18_II;
-#NET "ddr2_we_n" IOSTANDARD = SSTL18_II;
-#NET "ddr2_cs_n[*]" IOSTANDARD = SSTL18_II;
-#NET "ddr2_odt[*]" IOSTANDARD = SSTL18_II;
-#NET "ddr2_cke[*]" IOSTANDARD = SSTL18_II;
-#NET "ddr2_dm[*]" IOSTANDARD = SSTL18_II;
-#NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
-#NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
-#NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_II;
-#NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_II;
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: Clock Constraints
-##------------------------------------------------------------------------------
-NET "**/Clock" TNM_NET = "SYS_Clock";
-TIMESPEC "TS_SYS_Clock" = PERIOD "SYS_Clock" 5 ns HIGH 50 %;
-
-NET "**/ClockP90" TNM_NET = "SYS_ClockP90";
-TIMESPEC "TS_SYS_ClockP90" = PERIOD "SYS_ClockP90" 5 ns HIGH 50 %;
-
-NET "**/ClockD2" TNM_NET = "SYS_ClockD2";
-TIMESPEC "TS_SYS_ClockD2" = PERIOD "SYS_ClockD2" 7.5 ns HIGH 50 %;
-
-#NET "*/ClockF200" TNM_NET = "SYS_ClockF200";
-#TIMESPEC "TS_SYS_ClockF200" = PERIOD "SYS_ClockF200" 5 ns HIGH 50 %;
-##------------------------------------------------------------------------------
-
-##==============================================================================
-## Section: Controller 0
-## Desc: Memory Device: DDR2_SDRAM->SODIMMs->MT4HTF3264HY-53E
-## Data Width: 64
-## Data Mask: 1
-##==============================================================================
-
-##------------------------------------------------------------------------------
-## Section: IDELAYCTRL Location Constraints
-##------------------------------------------------------------------------------
-INST "**/*IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y2;
-INST "**/*IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;
-INST "**/*IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X0Y6;
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: Multicycle Paths
-## Desc: Define multicycle paths - these paths may take longer because
-## additional time allowed for logic to settle in
-## calibration/initialization FSM
-##------------------------------------------------------------------------------
+############################################################################
+
+############################################################################
+# Clock constraints #
+############################################################################
+
+NET "*/u_ddr2_infrastructure/sys_clk_ibufg" TNM_NET = "SYS_CLK";
+TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;
+
+NET "*/u_ddr2_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
+TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;
+
+############################################################################
+########################################################################
+# Controller 0
+# Memory Device: DDR2_SDRAM->SODIMMs->MT4HTF3264HY-53E #
+# Data Width: 64 #
+# Data Mask: 1 #
+########################################################################
+
+################################################################################
+# I/O STANDARDS
+################################################################################
+
+NET "ddr2_dq[*]" IOSTANDARD = SSTL18_II_DCI;
+NET "ddr2_a[*]" IOSTANDARD = SSTL18_II;
+NET "ddr2_ba[*]" IOSTANDARD = SSTL18_II;
+NET "ddr2_ras_n" IOSTANDARD = SSTL18_II;
+NET "ddr2_cas_n" IOSTANDARD = SSTL18_II;
+NET "ddr2_we_n" IOSTANDARD = SSTL18_II;
+NET "ddr2_cs_n[*]" IOSTANDARD = SSTL18_II;
+NET "ddr2_odt[*]" IOSTANDARD = SSTL18_II;
+NET "ddr2_cke[*]" IOSTANDARD = SSTL18_II;
+NET "ddr2_dm[*]" IOSTANDARD = SSTL18_II;
+#NET "sys_clk_p" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "sys_clk_n" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "clk200_p" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "clk200_n" IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+#NET "sys_rst_n" IOSTANDARD = LVCMOS18;
+#NET "phy_init_done" IOSTANDARD = LVCMOS18;
+#NET "error" IOSTANDARD = LVCMOS18;
+NET "ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
+NET "ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
+NET "ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_II;
+NET "ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_II;
+
+################################################################################
+# Location Constraints
+################################################################################
+
+NET "ddr2_dq[0]" LOC = "AF30" ; #Bank 17
+NET "ddr2_dq[1]" LOC = "AK31" ; #Bank 17
+NET "ddr2_dq[2]" LOC = "AF31" ; #Bank 17
+NET "ddr2_dq[3]" LOC = "AD30" ; #Bank 17
+NET "ddr2_dq[4]" LOC = "AJ30" ; #Bank 17
+NET "ddr2_dq[5]" LOC = "AF29" ; #Bank 17
+NET "ddr2_dq[6]" LOC = "AD29" ; #Bank 17
+NET "ddr2_dq[7]" LOC = "AE29" ; #Bank 17
+NET "ddr2_dq[8]" LOC = "AH27" ; #Bank 21
+NET "ddr2_dq[9]" LOC = "AF28" ; #Bank 21
+NET "ddr2_dq[10]" LOC = "AH28" ; #Bank 21
+NET "ddr2_dq[11]" LOC = "AA28" ; #Bank 21
+NET "ddr2_dq[12]" LOC = "AG25" ; #Bank 21
+NET "ddr2_dq[13]" LOC = "AJ26" ; #Bank 21
+NET "ddr2_dq[14]" LOC = "AG28" ; #Bank 21
+NET "ddr2_dq[15]" LOC = "AB28" ; #Bank 21
+NET "ddr2_dq[16]" LOC = "AC28" ; #Bank 21
+NET "ddr2_dq[17]" LOC = "AB25" ; #Bank 21
+NET "ddr2_dq[18]" LOC = "AC27" ; #Bank 21
+NET "ddr2_dq[19]" LOC = "AA26" ; #Bank 21
+NET "ddr2_dq[20]" LOC = "AB26" ; #Bank 21
+NET "ddr2_dq[21]" LOC = "AA24" ; #Bank 21
+NET "ddr2_dq[22]" LOC = "AB27" ; #Bank 21
+NET "ddr2_dq[23]" LOC = "AA25" ; #Bank 21
+NET "ddr2_dq[24]" LOC = "AC29" ; #Bank 17
+NET "ddr2_dq[25]" LOC = "AB30" ; #Bank 17
+NET "ddr2_dq[26]" LOC = "W31" ; #Bank 17
+NET "ddr2_dq[27]" LOC = "V30" ; #Bank 17
+NET "ddr2_dq[28]" LOC = "AC30" ; #Bank 17
+NET "ddr2_dq[29]" LOC = "W29" ; #Bank 17
+NET "ddr2_dq[30]" LOC = "V27" ; #Bank 17
+NET "ddr2_dq[31]" LOC = "W27" ; #Bank 17
+NET "ddr2_dq[32]" LOC = "V29" ; #Bank 17
+NET "ddr2_dq[33]" LOC = "Y27" ; #Bank 17
+NET "ddr2_dq[34]" LOC = "Y26" ; #Bank 17
+NET "ddr2_dq[35]" LOC = "W24" ; #Bank 17
+NET "ddr2_dq[36]" LOC = "V28" ; #Bank 17
+NET "ddr2_dq[37]" LOC = "W25" ; #Bank 17
+NET "ddr2_dq[38]" LOC = "W26" ; #Bank 17
+NET "ddr2_dq[39]" LOC = "V24" ; #Bank 17
+NET "ddr2_dq[40]" LOC = "R24" ; #Bank 19
+NET "ddr2_dq[41]" LOC = "P25" ; #Bank 19
+NET "ddr2_dq[42]" LOC = "N24" ; #Bank 19
+NET "ddr2_dq[43]" LOC = "P26" ; #Bank 19
+NET "ddr2_dq[44]" LOC = "T24" ; #Bank 19
+NET "ddr2_dq[45]" LOC = "N25" ; #Bank 19
+NET "ddr2_dq[46]" LOC = "P27" ; #Bank 19
+NET "ddr2_dq[47]" LOC = "N28" ; #Bank 19
+NET "ddr2_dq[48]" LOC = "M28" ; #Bank 19
+NET "ddr2_dq[49]" LOC = "L28" ; #Bank 19
+NET "ddr2_dq[50]" LOC = "F25" ; #Bank 19
+NET "ddr2_dq[51]" LOC = "H25" ; #Bank 19
+NET "ddr2_dq[52]" LOC = "K27" ; #Bank 19
+NET "ddr2_dq[53]" LOC = "K28" ; #Bank 19
+NET "ddr2_dq[54]" LOC = "H24" ; #Bank 19
+NET "ddr2_dq[55]" LOC = "G26" ; #Bank 19
+NET "ddr2_dq[56]" LOC = "G25" ; #Bank 19
+NET "ddr2_dq[57]" LOC = "M26" ; #Bank 19
+NET "ddr2_dq[58]" LOC = "J24" ; #Bank 19
+NET "ddr2_dq[59]" LOC = "L26" ; #Bank 19
+NET "ddr2_dq[60]" LOC = "J27" ; #Bank 19
+NET "ddr2_dq[61]" LOC = "M25" ; #Bank 19
+NET "ddr2_dq[62]" LOC = "L25" ; #Bank 19
+NET "ddr2_dq[63]" LOC = "L24" ; #Bank 19
+NET "ddr2_a[12]" LOC = "T31" ; #Bank 15
+NET "ddr2_a[11]" LOC = "R29" ; #Bank 15
+NET "ddr2_a[10]" LOC = "J31" ; #Bank 15
+NET "ddr2_a[9]" LOC = "R28" ; #Bank 15
+NET "ddr2_a[8]" LOC = "M31" ; #Bank 15
+NET "ddr2_a[7]" LOC = "P30" ; #Bank 15
+NET "ddr2_a[6]" LOC = "P31" ; #Bank 15
+NET "ddr2_a[5]" LOC = "L31" ; #Bank 15
+NET "ddr2_a[4]" LOC = "K31" ; #Bank 15
+NET "ddr2_a[3]" LOC = "P29" ; #Bank 15
+NET "ddr2_a[2]" LOC = "N29" ; #Bank 15
+NET "ddr2_a[1]" LOC = "M30" ; #Bank 15
+NET "ddr2_a[0]" LOC = "L30" ; #Bank 15
+NET "ddr2_ba[1]" LOC = "J30" ; #Bank 15
+NET "ddr2_ba[0]" LOC = "G31" ; #Bank 15
+NET "ddr2_ras_n" LOC = "H30" ; #Bank 15
+NET "ddr2_cas_n" LOC = "E31" ; #Bank 15
+NET "ddr2_we_n" LOC = "K29" ; #Bank 15
+NET "ddr2_cs_n[0]" LOC = "L29" ; #Bank 15
+NET "ddr2_odt[0]" LOC = "F31" ; #Bank 15
+NET "ddr2_cke[0]" LOC = "T28" ; #Bank 15
+NET "ddr2_dm[0]" LOC = "AJ31" ; #Bank 17
+NET "ddr2_dm[1]" LOC = "AE28" ; #Bank 21
+NET "ddr2_dm[2]" LOC = "Y24" ; #Bank 21
+NET "ddr2_dm[3]" LOC = "Y31" ; #Bank 17
+NET "ddr2_dm[4]" LOC = "V25" ; #Bank 17
+NET "ddr2_dm[5]" LOC = "P24" ; #Bank 19
+NET "ddr2_dm[6]" LOC = "F26" ; #Bank 19
+NET "ddr2_dm[7]" LOC = "J25" ; #Bank 19
+NET "sys_clk_p" LOC = "H14" ; #Bank 3
+NET "sys_clk_n" LOC = "H15" ; #Bank 3
+NET "clk200_p" LOC = "L19" ; #Bank 3
+NET "clk200_n" LOC = "K19" ; #Bank 3
+NET "sys_rst_n" LOC = "E9"; #Bank 20
+#NET "phy_init_done" LOC = "H18" ; #Bank 3
+NET "error" LOC = "F6"; #Bank 12
+NET "ddr2_dqs[0]" LOC = "AA29" ; #Bank 17
+NET "ddr2_dqs_n[0]" LOC = "AA30" ; #Bank 17
+NET "ddr2_dqs[1]" LOC = "AK28" ; #Bank 21
+NET "ddr2_dqs_n[1]" LOC = "AK27" ; #Bank 21
+NET "ddr2_dqs[2]" LOC = "AK26" ; #Bank 21
+NET "ddr2_dqs_n[2]" LOC = "AJ27" ; #Bank 21
+NET "ddr2_dqs[3]" LOC = "AB31" ; #Bank 17
+NET "ddr2_dqs_n[3]" LOC = "AA31" ; #Bank 17
+NET "ddr2_dqs[4]" LOC = "Y28" ; #Bank 17
+NET "ddr2_dqs_n[4]" LOC = "Y29" ; #Bank 17
+NET "ddr2_dqs[5]" LOC = "E26" ; #Bank 19
+NET "ddr2_dqs_n[5]" LOC = "E27" ; #Bank 19
+NET "ddr2_dqs[6]" LOC = "H28" ; #Bank 19
+NET "ddr2_dqs_n[6]" LOC = "G28" ; #Bank 19
+NET "ddr2_dqs[7]" LOC = "G27" ; #Bank 19
+NET "ddr2_dqs_n[7]" LOC = "H27" ; #Bank 19
+NET "ddr2_ck[0]" LOC = "AK29" ; #Bank 21
+NET "ddr2_ck_n[0]" LOC = "AJ29" ; #Bank 21
+NET "ddr2_ck[1]" LOC = "E28" ; #Bank 19
+NET "ddr2_ck_n[1]" LOC = "F28" ; #Bank 19
+
+################################################################################
+#IDELAYCTRL Location Constraints
+################################################################################
+
+INST "*/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;
+INST "*/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y2;
+INST "*/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X0Y6;
+
+###############################################################################
+# Define multicycle paths - these paths may take longer because additional
+# time allowed for logic to settle in calibration/initialization FSM
+###############################################################################
+
# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
# multicycle paths from originating flip-flop to ANY destination
# flip-flop (or in some cases, it can also be a BRAM)
# MUX Select for either rising/falling CLK0 for 2nd stage read capture
-INST "**/u_phy_calib/*gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
-TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS "TS_SYS_Clock" * 4;
-
+INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
+TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
+"TS_SYS_CLK" * 4;
# MUX select for read data - optional delay on data to account for byte skews
-#INST "*/u_usr_rd/*gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
-#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS "TS_SYS_Clock" * 4;
-
+#INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
+#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
+#"TS_SYS_CLK" * 4;
# Calibration/Initialization complete status flag (for PHY logic only) - can
# be used to drive both flip-flops and BRAMs
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
-TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS "TS_SYS_Clock" * 4;
-TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS "TS_SYS_Clock" * 4;
-
+TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
+"TS_SYS_CLK" * 4;
+TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
+"TS_SYS_CLK" * 4;
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
-INST "**/u_phy_calib/*gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
-TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_Clock" * 4;
-INST "**/u_phy_calib/*gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
-TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_Clock" * 4;
-INST "**/u_phy_calib/*gen_cal_rden_dly*.u_ff_cal_rden_dly" TNM = "TNM_CAL_RDEN_DLY";
-TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS "TS_SYS_Clock" * 4;
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: DQS Squelch Constraints
-## Desc: DQS Read Post amble Glitch Squelch circuit related constraints
-## LOC placement of DQS-squelch related IDDR and IDELAY elements
-## Each circuit can be located at any of the following locations:
-## 1. Unused "N"-side of DQS differential pair I/O
-## 2. DM data mask (output only, input side is free for use)
-## 3. Any output-only site
-##------------------------------------------------------------------------------
-INST "**/*gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96";
-INST "**/*gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96";
-INST "**/*gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58";
-INST "**/*gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58";
-INST "**/*gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
-INST "**/*gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
-INST "**/*gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100";
-INST "**/*gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100";
-INST "**/*gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";
-INST "**/*gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";
-INST "**/*gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";
-INST "**/*gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";
-INST "**/*gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
-INST "**/*gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
-INST "**/*gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
-INST "**/*gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: DQS CE LOCs
-## Desc: LOC and timing constraints for flop driving DQS CE enable signal
-## from fabric logic. Even though the absolute delay on this path
-## is calibrated out (when synchronizing this output to DQS), the
-## delay should still be kept as low as possible to reduce
-## post-calibration voltage/temp variations - these are roughly
-## proportional to the absolute delay of the path
-##------------------------------------------------------------------------------
-INST "**/u_phy_calib/*gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48;
-INST "**/u_phy_calib/*gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29;
-INST "**/u_phy_calib/*gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31;
-INST "**/u_phy_calib/*gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50;
-INST "**/u_phy_calib/*gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;
-INST "**/u_phy_calib/*gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;
-INST "**/u_phy_calib/*gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;
-INST "**/u_phy_calib/*gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: DQS Gate Control
-## Desc: Control for DQS gate - from fabric flop. Prevent "runaway"
-## delay - two parts to this path: (1) from fabric flop to IDELAY,
-## (2) from IDELAY to asynchronous reset of IDDR that drives the DQ
-## CE's. This can be relaxed by the user for lower frequencies:
-## 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
-## In general PAR should be able to route this within 900ps over
-## all speed grades.
-##------------------------------------------------------------------------------
-NET "**/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
-NET "**/u_phy_io/*gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: IDDR Half Cycles
-## Desc: "Half-cycle" path constraint from IDDR to CE pin for all DQ
-## IDDR's for DQS Read Post amble Glitch Squelch circuit.
-##------------------------------------------------------------------------------
+INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
+TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;
+INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
+TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;
+INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
+ TNM = "TNM_CAL_RDEN_DLY";
+TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
+ "TS_SYS_CLK" * 4;
+
+###############################################################################
+# DQS Read Post amble Glitch Squelch circuit related constraints
+###############################################################################
+
+###############################################################################
+# LOC placement of DQS-squelch related IDDR and IDELAY elements
+# Each circuit can be located at any of the following locations:
+# 1. Unused "N"-side of DQS differential pair I/O
+# 2. DM data mask (output only, input side is free for use)
+# 3. Any output-only site
+###############################################################################
+
+INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96";
+INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96";
+INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58";
+INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58";
+INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
+INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
+INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100";
+INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100";
+INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";
+INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";
+INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";
+INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";
+INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
+INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
+INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
+INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
+
+###############################################################################
+# LOC and timing constraints for flop driving DQS CE enable signal
+# from fabric logic. Even though the absolute delay on this path is
+# calibrated out (when synchronizing this output to DQS), the delay
+# should still be kept as low as possible to reduce post-calibration
+# voltage/temp variations - these are roughly proportional to the
+# absolute delay of the path
+###############################################################################
+
+INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48;
+INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29;
+INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31;
+INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50;
+INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;
+INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;
+INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;
+INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;
+
+# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
+# two parts to this path: (1) from fabric flop to IDELAY, (2) from
+# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
+# This can be relaxed by the user for lower frequencies:
+# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
+# In general PAR should be able to route this
+# within 900ps over all speed grades.
+NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
+NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
+
+###############################################################################
+# "Half-cycle" path constraint from IDDR to CE pin for all DQ IDDR's
+# for DQS Read Post amble Glitch Squelch circuit
+###############################################################################
+
# Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
# where slack account for rise-time of DQS on board. For now assume slack =
# 0.400ns (based on initial SPICE simulations, assumes use of ODT), so
# time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
-INST "**/*gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
-INST "**/*gen_dq[*].u_iob_dq/*gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
+INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
+INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: Area Group
-## Desc: MIG 2.2: Prevent unrelated logic from being packed into any
-## slices used by read data capture RPM's - if unrelated logic gets
-## packed into these slices, it could cause the DIRT strings that
-## define the IDDR -> fabric flop routing to become unroutable
-## during PAR stage (unrelated logic may require routing resources
-## required by the DIRT strings - MAP does not currently take into
-## account DIRT strings when placing logic
-##------------------------------------------------------------------------------
+
+###############################################################################
+# MIG 2.2: Prevent unrelated logic from being packed into any slices used
+# by read data capture RPM's - if unrelated logic gets packed into
+# these slices, it could cause the DIRT strings that define the
+# IDDR -> fabric flop routing to become unroutable during PAR stage
+# (unrelated logic may require routing resources required by the
+# DIRT strings - MAP does not currently take into account DIRT
+# strings when placing logic
+###############################################################################
+
AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
-##------------------------------------------------------------------------------
-
-##------------------------------------------------------------------------------
-## Section: DQ LOC Constraints
-## Desc: Location constraints for DQ read-data capture flops in fabric
-## (for 2nd stage capture)
-##------------------------------------------------------------------------------
-INST "**/*gen_dq[0].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
-INST "**/*gen_dq[1].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43;
-INST "**/*gen_dq[2].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45;
-INST "**/*gen_dq[3].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
-INST "**/*gen_dq[4].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41;
-INST "**/*gen_dq[5].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
-INST "**/*gen_dq[6].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
-INST "**/*gen_dq[7].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
-INST "**/*gen_dq[8].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
-INST "**/*gen_dq[9].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32;
-INST "**/*gen_dq[10].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
-INST "**/*gen_dq[11].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
-INST "**/*gen_dq[12].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26;
-INST "**/*gen_dq[13].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
-INST "**/*gen_dq[14].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
-INST "**/*gen_dq[15].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
-INST "**/*gen_dq[16].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35;
-INST "**/*gen_dq[17].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
-INST "**/*gen_dq[18].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
-INST "**/*gen_dq[19].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
-INST "**/*gen_dq[20].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
-INST "**/*gen_dq[21].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37;
-INST "**/*gen_dq[22].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
-INST "**/*gen_dq[23].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
-INST "**/*gen_dq[24].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
-INST "**/*gen_dq[25].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
-INST "**/*gen_dq[26].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53;
-INST "**/*gen_dq[27].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55;
-INST "**/*gen_dq[28].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
-INST "**/*gen_dq[29].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
-INST "**/*gen_dq[30].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
-INST "**/*gen_dq[31].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
-INST "**/*gen_dq[32].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
-INST "**/*gen_dq[33].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
-INST "**/*gen_dq[34].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
-INST "**/*gen_dq[35].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
-INST "**/*gen_dq[36].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
-INST "**/*gen_dq[37].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57;
-INST "**/*gen_dq[38].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
-INST "**/*gen_dq[39].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
-INST "**/*gen_dq[40].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
-INST "**/*gen_dq[41].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
-INST "**/*gen_dq[42].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122;
-INST "**/*gen_dq[43].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
-INST "**/*gen_dq[44].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
-INST "**/*gen_dq[45].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
-INST "**/*gen_dq[46].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
-INST "**/*gen_dq[47].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
-INST "**/*gen_dq[48].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
-INST "**/*gen_dq[49].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
-INST "**/*gen_dq[50].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132;
-INST "**/*gen_dq[51].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
-INST "**/*gen_dq[52].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125;
-INST "**/*gen_dq[53].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
-INST "**/*gen_dq[54].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
-INST "**/*gen_dq[55].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
-INST "**/*gen_dq[56].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
-INST "**/*gen_dq[57].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
-INST "**/*gen_dq[58].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137;
-INST "**/*gen_dq[59].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
-INST "**/*gen_dq[60].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135;
-INST "**/*gen_dq[61].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
-INST "**/*gen_dq[62].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
-INST "**/*gen_dq[63].u_iob_dq/*gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139;
-##------------------------------------------------------------------------------
+
+###############################################################################
+# Location constraints for DQ read-data capture flops in fabric (for 2nd
+# stage capture)
+###############################################################################
+
+INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; # AF30 X0Y22 *
+INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43; # AK31 X0Y23
+INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45; # AF31 X0Y25
+INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; # AD30 X0Y26
+INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41; # AJ30 X0Y21
+INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42; # AF29 X0Y22 ***
+INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; # AD29 X0Y24
+INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44; # AE29 X0Y24
+INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; # AH27 X0Y8 ***
+INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32; # AF28 X0Y12
+INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; # AH28 X0Y13
+INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; # AA28 X0Y14
+INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26; # AG25 X0Y6
+INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28; # AJ26 X0Y8 *
+INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33; # AG28 X0Y13
+INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34; # AB28 X0Y14
+INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35; # AC28 X0Y15
+INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; # AB25 X0Y16 ***
+INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; # AC27 X0Y18
+INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; # AA26 X0Y19
+INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36; # AB26 X0Y16 *
+INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37; # AA24 X0Y17
+INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38; # AB27 X0Y18
+INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39; # AA25 X0Y19
+INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46; # AC29 X0Y26
+INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; # AB30 X0Y29 ***
+INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53; # W31 X0Y33
+INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55; # V30 X0Y35
+INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49; # AC30 X0Y29 *
+INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; # W29 X0Y32
+INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; # V27 X0Y34 ***
+INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; # W27 X0Y36
+INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52; # V29 X0Y32
+INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56; # Y27 X0Y36
+INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; # Y26 X0Y38
+INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; # W24 X0Y39
+INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54; # V28 X0Y34 *
+INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57; # W25 X0Y37
+INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58; # W26 X0Y38
+INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59; # V24 X0Y39
+INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; # R24 X0Y100
+INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; # P25 X0Y101
+INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122; # N24 X0Y102
+INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; # P26 X0Y103
+INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120; # T24 X0Y100
+INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121; # N25 X0Y101
+INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123; # P27 X0Y103
+INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; # N28 X0Y104
+INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124; # M28 X0Y104
+INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; # L28 X0Y106
+INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132; # F25 X0Y112
+INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; # H25 X0Y113
+INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125; # K27 X0Y105
+INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126; # K28 X0Y106
+INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133; # H24 X0Y113
+INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; # G26 X0Y114
+INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134; # G25 X0Y114
+INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; # M26 X0Y116
+INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137; # J24 X0Y117
+INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; # L26 X0Y118
+INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135; # J27 X0Y115
+INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136; # M25 X0Y116
+INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138; # L25 X0Y118
+INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139; # L24 X0Y119
+
projects / fleet.git / blobdiff