migrate verilog into ship files

[fleet.git] / src / edu / berkeley / fleet / slipway / alu1.v

diff --git a/src/edu/berkeley/fleet/slipway/alu1.v b/src/edu/berkeley/fleet/slipway/alu1.v
index 89659be..ac813d0 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/alu1.v
+++ b/src/edu/berkeley/fleet/slipway/alu1.v
@@ -40,3 +40,6 @@ module alu1 (clk,
   end
 
 endmodule
+
+
+