migrate verilog into ship files

[fleet.git] / src / edu / berkeley / fleet / slipway / fifo.v

diff --git a/src/edu/berkeley/fleet/slipway/fifo.v b/src/edu/berkeley/fleet/slipway/fifo.v
index 235349c..6bff619 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/fifo.v
+++ b/src/edu/berkeley/fleet/slipway/fifo.v
@@ -23,3 +23,5 @@ module fifo (clk,
   fifo4 s4(clk, r34,  a34,  d34,  out_r, out_a, out_d);
 
 endmodule
+
+