massive overhaul of slipway (fpga-fleet)

[fleet.git] / src / edu / berkeley / fleet / slipway / fifo4.v

diff --git a/src/edu/berkeley/fleet/slipway/fifo4.v b/src/edu/berkeley/fleet/slipway/fifo4.v
index 1ffe1ae..7045739 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/fifo4.v
+++ b/src/edu/berkeley/fleet/slipway/fifo4.v
@@ -9,12 +9,12 @@ module fifo4 (clk,
   input out_a;
   output in_a;
   output out_r;
-  input [(`DATAWIDTH-1):0] in_d;
-  output [(`DATAWIDTH-1):0] out_d;
+  input [(`PACKET_WIDTH-1):0] in_d;
+  output [(`PACKET_WIDTH-1):0] out_d;
 
-  wire [(`DATAWIDTH-1):0] d12;
-  wire [(`DATAWIDTH-1):0] d23;
-  wire [(`DATAWIDTH-1):0] d34;
+  wire [(`PACKET_WIDTH-1):0] d12;
+  wire [(`PACKET_WIDTH-1):0] d23;
+  wire [(`PACKET_WIDTH-1):0] d34;
 
   fifostage s1(clk, in_r, in_a, in_d, r12, a12,     d12);
   fifostage s2(clk, r12,  a12,  d12,  r23, a23,     d23);