massive overhaul of slipway (fpga-fleet)

[fleet.git] / src / edu / berkeley / fleet / slipway / fifostage.v

diff --git a/src/edu/berkeley/fleet/slipway/fifostage.v b/src/edu/berkeley/fleet/slipway/fifostage.v
index 64d8e6d..35d8033 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/fifostage.v
+++ b/src/edu/berkeley/fleet/slipway/fifostage.v
@@ -5,9 +5,9 @@ module fifostage (clk,
                       out_r_, out_a, out_d_);
 
   input  clk;
-  `input( in_r,   in_a,   in_a_, [(`DATAWIDTH-1):0], in_d)
-  `output(out_r,  out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-  `defreg(out_d_,                [(`DATAWIDTH-1):0], out_d)
+  `input( in_r,   in_a,   in_a_, [(`PACKET_WIDTH-1):0], in_d)
+  `output(out_r,  out_r_, out_a, [(`PACKET_WIDTH-1):0], out_d_)
+  `defreg(out_d_,                [(`PACKET_WIDTH-1):0], out_d)
 
   reg full;