fixed memory ship, fpga implementation now works

[fleet.git] / tests / memory / count.and.stride.fleet

diff --git a/tests/memory/count.and.stride.fleet b/tests/memory/count.and.stride.fleet
index 505f9c2..e56402a 100644 (file)
--- a/tests/memory/count.and.stride.fleet
+++ b/tests/memory/count.and.stride.fleet
@@ -12,20 +12,21 @@
 
 // dumb configurations
 debug.in:        [*] take, deliver;
-memory.inAddr:   [*] take, deliver;
-memory.inData:   [*] take, deliver;
+memory.inAddrRead:   [*] take, deliver;
+memory.inAddrWrite:   [*] take, deliver;
+memory.inDataWrite:   [*] take, deliver;
 memory.inCount:  [*] take, deliver;
 memory.inStride: [*] take, deliver;
 fifo.in:         [*] take, deliver;
 
 // addresses and values to initialize the memory with
-1:  sendto memory.inAddr.writeMany;
+1:  sendto memory.inAddrWrite;
 4:  sendto memory.inCount;
 1:  sendto memory.inStride;
-11: sendto memory.inData;
-12: sendto memory.inData;
-13: sendto memory.inData;
-14: sendto memory.inData;
+11: sendto memory.inDataWrite;
+12: sendto memory.inDataWrite;
+13: sendto memory.inDataWrite;
+14: sendto memory.inDataWrite;
 
 // send write-completion tokens to the fifo output
 memory.out:
@@ -36,7 +37,7 @@ memory.out:
 // the read addresses
 fifo.out:
   [4] wait;
-  take, sendto memory.inAddr.readMany;
+  take, sendto memory.inAddrRead;
 
 // read addresses
 4: sendto fifo.in;