fixed memory ship, fpga implementation now works

[fleet.git] / tests / memory / memory-test.fleet

diff --git a/tests/memory/memory-test.fleet b/tests/memory/memory-test.fleet
index 16d4d4b..747e5ae 100644 (file)
--- a/tests/memory/memory-test.fleet
+++ b/tests/memory/memory-test.fleet
@@ -1,5 +1,4 @@
 // output ///////////////////////////////////////////////////////////////////
-#skip
 #expect 14
 #expect 13
 #expect 12
@@ -11,31 +10,32 @@
 #ship fifo         : Fifo
 
 // dumb configurations
-debug.in:        [*] take, deliver;
-memory.inAddr:   [*] take, deliver;
-memory.inData:   [*] take, deliver;
-fifo.in:         [*] take, deliver;
-
-// addresses and values to initialize the memory with
-1:  sendto memory.inAddr.write;
-2:  sendto memory.inAddr.write;
-3:  sendto memory.inAddr.write;
-4:  sendto memory.inAddr.write;
-11: sendto memory.inData;
-12: sendto memory.inData;
-13: sendto memory.inData;
-14: sendto memory.inData;
+debug.in:           [*] take, deliver;
+memory.inAddrRead:  [*] take, deliver;
+memory.inAddrWrite: [*] take, deliver;
+memory.inDataWrite: [*] take, deliver;
+fifo.in:            [*] take, deliver;
 
 // send write-completion tokens to the fifo output
 memory.out:
   [4] take, notify fifo.out;
   [*] take, sendto debug.in;
 
+// addresses and values to initialize the memory with
+1:  sendto memory.inAddrWrite;
+2:  sendto memory.inAddrWrite;
+3:  sendto memory.inAddrWrite;
+4:  sendto memory.inAddrWrite;
+11: sendto memory.inDataWrite;
+12: sendto memory.inDataWrite;
+13: sendto memory.inDataWrite;
+14: sendto memory.inDataWrite;
+
 // when the write-completion tokens accumulate, unleash
 // the read addresses
 fifo.out:
   [4] wait;
-  [4] take, sendto memory.inAddr.read;
+  [4] take, sendto memory.inAddrRead;
 
 // read addresses
 4:  sendto fifo.in;