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some cleanups, build fpga stuff in build/fpga, not src
[fleet.git]
/
ships
/
Alu2.ship
2007-08-16
adam
update tests in ship files
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commitdiff
2007-08-12
adam
run all tests (including ships directory), add #skip...
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2007-07-03
adam
updates to ship documentation
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2007-02-25
adam
add Alu3 ship and tests
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2007-02-25
adam
rename ItemForShip to DataForShip for consistency
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2007-02-22
adam
update ships for overhaul
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2007-02-17
adam
add ship specific literals and a test case
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2007-02-16
adam
added MAX and MIN on Alu2 ship
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2007-02-13
adam
autogenerate parts of Alu1, Alu2, Lut3 verilog
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2007-02-13
adam
cleanup on Alu2
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2007-02-13
adam
factor out verilog headers on Alu2 ship
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2007-02-13
adam
added comments to ship files
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2007-02-12
adam
change igor/archsim to fleetsim
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2007-02-12
adam
update everything to naming conventions agreed upon...
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2007-02-12
adam
migrate verilog into ship files
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2007-02-12
adam
add more ship files
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