fleet.git
2009-06-05 jlexauadded vdd/gnd exports at corner of esd block
2009-06-05 jlexauupdate from Adam
2009-06-05 jlexauupdates from Adam, plus DRC fixes
2009-06-04 Adam Megaczstuff
2009-06-04 jlexaufixed ERC error in pads_north
2009-06-02 ac150875fixed erc errors
2009-06-02 jlexauchanged config_input to fix DRC/ERC errors
2009-06-02 jlexaudeleted twinNand{lay} at Ivan's suggestion
2009-06-02 Adam Megaczkesselscounter passes ncc, drc
2009-06-02 jlexauCreated project settings to get the GDS layers correct.
2009-06-02 Adam MegaczkesselCounter layout complete, passes NCC and DRC
2009-05-30 jlexaurevised dummy exclusion layers for core
2009-05-29 jlexauadded Alex's ESD experiment (LVS fixes)
2009-05-29 jlexauadding Alex's ESD experiment to top level
2009-05-29 jlexaulatest files from Ivan plus top-level hookup
2009-05-29 Adam Megaczbroke out ripple-carry logic into a separate module...
2009-05-29 Adam Megaczremove inversion from kessels OLC scan (and special...
2009-05-29 Adam Megaczsimplify ripple-carry logic
2009-05-29 Adam Megaczmake test 6 harder
2009-05-29 Adam Megacztest updates for kessels counter
2009-05-29 Adam Megaczproper decoding of kessels OLC scan
2009-05-29 Adam Megaczbetter debugging messages on ProperStopper
2009-05-29 Adam Megaczadd hsim gunk to header.hsp
2009-05-29 Adam Megaczkessels passes all tests, hsim+verilog
2009-05-28 ac150875added fill
2009-05-28 ac150875added fill
2009-05-28 ac150875top level with ivan's fill
2009-05-28 ac150875top level with ivan's fill
2009-05-28 Adam Megaczupdates for kessels counter
2009-05-28 Adam Megaczchanges for kesselsCounter, flip initial state of D...
2009-05-28 Adam Megaczcheckpoint2: pre-sizing
2009-05-28 Adam Megaczcheckpoint1
2009-05-28 Adam Megaczremove now-auto-generated files
2009-05-28 Adam Megaczadd verilog/spice generation to marina.bsh
2009-05-28 Adam Megaczkessels bugfixes
2009-05-28 Adam Megaczadd useHsim option
2009-05-28 Adam Megacznew marina.xml
2009-05-28 Adam Megaczmarina.bsh updates for new scanCellFtaller
2009-05-27 ac150875top level with ivan's fill
2009-05-27 Adam Megaczadd kesselsCounter.jelib
2009-05-26 jlexaulatest files from Ivan
2009-05-21 Adam Megaczupdates from ivan
2009-05-21 Adam Megacznew files from ivan
2009-05-19 Adam Megaczfixes to break apart layout cells
2009-05-19 Adam Megacztest fixes
2009-05-15 ac150875Top level passes DRC/LVS, minus density errors
2009-05-15 ac150875Basic layout of top level ESD
2009-05-15 ac150875Some basic cells for ESD pads
2009-05-15 ac150875Layout of pads for ESD test
2009-05-15 ac150875Schematics and icons of pads for ESD test
2009-05-15 ac150875orange library for ESD pads ONLY
2009-05-15 ac150875ESD pad library
2009-05-15 ac150875basic library cells for ESD
2009-05-14 Adam Megaczfix adams blunders
2009-05-14 Adam Megaczbreak apart scanCellF and scanFx3 multiple layouts
2009-05-13 Adam Megacznew files from ivan, 12-May
2009-05-13 Adam Megaczupdate tests
2009-05-10 Adam Megacznew files from ivan, all tests pass
2009-05-06 Adam Megaczprint instruction being inserted, remove unnecessary...
2009-05-06 Adam Megaczadd Marina.dispatch(Instruction[]) and Marina.Ilc.toStr...
2009-05-04 Adam Megacznew files from Ivan, 04-May
2009-05-04 Adam Megaczcheckin
2009-05-04 Adam Megacznew files from ivan, test updates
2009-05-03 Adam Megaczupdate with new files from Ivan, 02-May-2009
2009-05-01 Adam Megaczfix handling of capture clock
2009-05-01 Adam Megacznew files from Ivan, 30-Apr
2009-04-30 Adam Megacznew files from ivan, 29-Apr, all tests pass
2009-04-29 Adam Megacznew files from ivan
2009-04-29 Adam Megaczadd package.html
2009-04-29 Adam Megaczadd DeferredBitVector.java
2009-04-29 megaczfix spacing in Instruction.toString()
2009-04-29 Adam Megaczadd explicit name parameter to proper stoppers, better...
2009-04-28 Adam Megaczmove latest files into experimental-branch
2009-04-28 jlexaunew libraries from Ivan - 28 April 2009
2009-04-28 Adam Megaczupdate marina.{spi,v}
2009-04-28 Adam Megaczadd extra pair of inverters to fire[do] signal in ohPredDo
2009-04-28 Adam Megaczadd verilog hint for wired-or
2009-04-24 Adam Megaczundo accidental checkin
2009-04-24 Adam Megaczall tests pass except requeue stage tests
2009-04-24 Adam Megaczadd MarinaPacket.null_word
2009-04-24 Adam Megaczdisable traceFill/traceDrain
2009-04-24 Adam Megaczimplement InstructionStopper.fillTorpedo()
2009-04-23 Adam Megacznew files from ivan, 22-Apr
2009-04-23 Adam Megaczmore tests pass now
2009-04-23 Adam Megaczencoding bugfix
2009-04-21 Adam Megaczmore tests pass now
2009-04-21 Adam Megaczmore tests pass now
2009-04-21 Adam Megaczfix another encoding bug
2009-04-21 Adam Megacznew files from ivan
2009-04-21 Adam Megaczupdate with new files 20-Apr from Ivan, regenerate...
2009-04-21 Adam Megaczupdate instruction encoding bug
2009-04-21 Adam Megaczfix ILC tests, take advantage of new command line flags...
2009-04-21 Adam Megaczsome ILC fixes
2009-04-20 Adam Megaczadd additional masterClear() code for Verilog simulations
2009-04-20 Adam Megaczadd command-line arguments for -verilog and -testChains
2009-04-20 Adam Megaczupdate some paths, add master clear code for Verilog...
2009-04-20 Adam Megaczmake null_path public
2009-04-20 Adam Megaczremove drainNoCheck() hack from InstructionStopper
2009-04-19 Adam Megaczenable clockHack for VerilogModel
2009-04-19 Adam Megaczlatest files from ivan
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