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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
71 & \color{red} Roll back ``Distinguish {\tt Z}-flag from OLC=0'' \\
72 & \color{red} Clarify what ``{\tt X-Extended}'' means \\
74 & Distinguish {\tt Z}-flag from OLC=0\\
75 & Add {\tt flush} instruction\\
76 & Change {\t I} bit from ``Interruptable'' to ``Immune''\\
78 & Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
80 & Note that decision to requeue is based on value of OLC {\it before} execution\\
81 & Note that decision to open the hatch is based on value of {\tt OS} bit\\
83 & Added {\tt OLC=0} predicate \\
84 & Eliminated {\tt TAPL} (made possible by previous change) \\
85 & Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\
87 & Fixed a few typos \\
88 & Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
89 & Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
91 & When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
92 & Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
94 & Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
95 & Reworked encoding of {\tt set} instruction \\
98 & Factored in Russell Kao's comments (thanks!)\\
99 & Added mechanism for setting C-flag from fabric even on outboxes\\
101 %& Made {\tt OLC} test a predicate-controlled condition\\
102 %& Rewrote ``on deck'' section \\
103 %& Added ``{\tt unset}'' value for {\tt ILC}\\
104 %& Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
107 %& added comment about address-to-path ship \\
108 %& changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
109 %& changed the order of instructions in the encoding map \\
111 %& added epilogue fifo to diagrams \\
112 %& indicated that a token sent to the instruction port is treated as a torpedo \\
114 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
115 %& replaced {\tt literal} with {\tt shift} instruction \\
117 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
118 %& Removed ability to manually set the {\tt C} flag \\
119 %& Expanded predicate field to three bits \\
120 %& New literals scheme (via shifting) \\
121 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
122 %& Added summary of instruction encodings on last page \\
124 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
126 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
127 %& update table 3.1.2 \\
128 %& rename {\tt S} flag to {\tt C} \\
129 %& noted that {\tt setFlags} can be used as {\tt nop} \\
131 %& removed the {\tt L} flag (epilogues can now do this) \\
132 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
133 %& renamed {\tt data} instruction to {\tt literal} \\
134 %& renamed {\tt send} instruction to {\tt move} \\
136 %& added ``if its predicate is true'' to repeat count \\
137 %& added note that red wires do not contact ships \\
138 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
139 %& removed black dot from diagrams \\
140 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
141 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
142 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
143 %& added section ``Torpedo Details'' \\
144 %& removed {\tt torpedo} instruction \\
147 %& renamed loop+repeat to outer+inner (not in red) \\
148 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
149 %& rewrote ``inner and outer loops'' section \\
150 %& updated all diagrams \\
153 %& Moved address bits to the LSB-side of a 37-bit instruction \\
154 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
155 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
156 %& Created the {\tt Hold} field \\
157 %& Changed how ReLooping works \\
158 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
165 \epsfig{file=all,height=1.5in}
166 \epsfig{file=overview-new,height=1.5in}
171 \section{Overview of Fleet}
173 A Fleet processor is organized around a {\it switch fabric}, which is
174 a packet-switched network with reliable in-order delivery. The switch
175 fabric is used to carry data between different functional units,
176 called {\it ships}. Each ship is connected to the switch fabric by
177 one or more programmable elements known as {\it docks}.
179 A {\it path} specifies a route through the switch fabric from a
180 particular {\it source} to a particular {\it destination}. The
181 combination of a path and a single word to be delivered is called a
182 {\it packet}. The switch fabric carries packets from their sources to
183 their destinations. Each dock has two destinations: one for {\it
184 instructions} and one for {\it data}. A Fleet is programmed by
185 depositing instruction packets into the switch fabric with paths that
186 will lead them to instruction destinations of the docks at which they
189 When a packet arrives at the instruction destination of a dock, it is
190 enqueued for execution. Before the instruction executes, it may cause
191 the dock to wait for a packet to arrive at the dock's data destination
192 or for a value to be presented by the ship. When an instruction
193 executes it may consume this data and may present a data value to the
194 ship or transmit a packet.
196 When an instruction sends a packet into the switch fabric, it may
197 specify that the payload of the packet is irrelevant. Such packets
198 are known as {\it tokens}, and consume less energy than data packets.
202 \epsfig{file=overview-new,width=2.5in}\\
203 {\it Overview of a Fleet processor; dark gray shading represents the
204 switch fabric, ships are shown in light gray, and docks are shown in blue.}
210 \section{The FleetTwo Dock}
212 The diagram below represents a conceptual view of the interface
213 between ships and the switch fabric; actual implementation circuitry
217 \epsfig{file=all,width=3.5in}\\
218 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
219 blue lines carry either tokens or data words, red lines carry either
220 instructions or torpedoes, and dashed lines carry only tokens.}
223 Each dock consists of a {\it data latch}, which is as wide as a single
224 machine word and a {\it pump}, which is a circular fifo of
225 instruction-width latches. The values in the pump control the data
226 latch. The dock also includes a {\it path latch}, which
227 stores the path along which outgoing packets will be sent.\color{black}
229 Note that the pump in each dock has a destination of its own; this is
230 the {\it instruction destination} mentioned in the previous section.
232 From any source to any dock's data destination there are
233 two distinct paths which differ by a single bit. This bit is known as
234 the ``signal'' bit, and the routing of a packet is not affected by it;
235 the signal bit is used to pass control values between docks. Note that paths
236 terminating at an {\it instruction} destination need not have a signal
240 \section{Instructions}
242 In order to cause an instruction to execute, the programmer must first
243 arrange for that instruction word to arrive in the data latch of some
244 output dock. For example, this might be the ``data read'' output dock
245 of the memory access ship or the output of a fifo ship. Once an
246 instruction has arrived at this output dock, it is {\it dispatched} by
247 sending it to the {\it instruction port} of the dock at which it is to
250 Each instruction is 26 bits long, which makes it possible for an
251 instruction and an 11-bit path to fit in a single word of memory.
252 This path is the path from the {\it dispatching} dock to the {\it
255 \setlength{\bitwidth}{3.5mm}
257 \begin{bytefield}{37}
258 \bitheader[b]{0,10,11,36}\\
259 \bitbox{26}{instruction}
260 \bitbox{11}{dispatch path}
266 \subsection{Life Cycle of an Instruction}
268 The diagram below shows an input dock for purposes of illustration:
271 \epsfig{file=in,width=4in}\\
278 \epsfig{file=out,width=4in}\\
282 \subsubsection{Torpedoes}
284 A token sent to an instruction destination is called a {\it torpedo}.
285 When a torpedo arrives at the tail of {\tt EF}, it is deposited in a
286 waiting area (not shown) rather than being enqueued into {\tt EF}.
288 \subsection{Format of an Instruction}
290 All instruction words have the following format:
292 \newcommand{\bitsHeader}{
297 \newcommand{\bitsHeaderNoI}{
303 \setlength{\bitwidth}{3.5mm}
305 \begin{bytefield}{37}
306 \bitheader[b]{0,10,11,31,32,34-36}\\
311 \bitbox{11}{dispatch path}
317 \item The {\tt I} bit stands for {\tt Immune},
318 and indicates if an instruction is
319 immune to torpedoes. This bit only appears
320 in {\tt move} instructions.
322 \item The {\tt OS} (``One Shot'') bit indicates whether or not this
323 instruction can pass through the pump more than once. If set to
324 {\tt 1}, then the instruction is a ``one-shot'' instruction, and
325 does not pass through the instruction fifo more than once.
327 \item The {\tt P} bits are a {\it predicate}; this
328 holds a code which indicates if the instruction should be executed or
329 ignored depending on the state of flags in the dock.
333 \subsection{Loop Counters}
335 A programmer can perform two types of loops: {\it inner} loops of only
336 one instruction and {\it outer} loops of multiple instructions. Inner
337 loops may be nested within an outer loop, but no other nesting of
340 The dock has two loop counters, one for each kind of loop:
343 \item {\tt OLC} is the Outer Loop Counter
344 \item {\tt ILC} is the Inner Loop Counter
347 The {\tt OLC} applies to all instructions and can hold integers {\tt
350 The {\tt ILC} applies only to {\tt move} instructions and can hold
351 integers {\tt 0..MAX_ILC} as well as a special value: $\infty$. When
352 {\tt ILC=0} the next {\tt move} instruction executes zero times (ie is
353 ignored). When {\tt ILC=$\infty$} the next {\tt move} instruction
354 executes until interrupted by a torpedo. After every {\tt move}
355 instruction the {\tt ILC} is reset to {\tt 1} (note that it is reset
356 to {\tt 1}, {\it not to 0}).
359 \subsection{Flags and Predication}
361 The pump has four flags: {\tt A}, {\tt B},
362 {\tt C}, and {\tt Z}.
365 \item The {\tt A} and {\tt B} flags are general-purpose flags which
366 may be set and cleared by the programmer.
370 % The {\tt L} flag, known as the {\it last} flag, is set whenever
371 % the value in the outer counter ({\tt OLC}) is one,
374 % that the dock is in the midst of the last iteration of an
375 % outer loop. This flag can be used to perform certain
376 % operations (such as sending a completion token) only on the last
377 % iteration of an outer loop.
379 \item The {\tt C} flag is known as the {\it control} flag, and may be
380 set by the {\tt move} instruction based on information from the
381 ship or from an inbound packet. See the {\tt move} instruction
386 \item The {\tt Z} flag is known as the {\it zero} flag; it is set
387 whenever the {\tt OLC} is zero, and is cleared whenever the {\tt
394 The {\tt P} field specifies a three-bit {\it predicate}. The
395 predicate determines which conditions must be true in order for the
396 instruction to execute; if it is not executed, it is simply {\it
397 ignored}. The table below shows what conditions must be true in
398 order for an instruction to execute:
401 \begin{tabular}{|r|l|}\hline
402 Code & Execute if \\\hline
403 {\tt 000:} & {\tt Z=0}\ and {\tt A=0} \\
404 {\tt 001:} & {\tt Z=0}\ and {\tt A=1} \\
405 {\tt 010:} & {\tt Z=0}\ and {\tt B=0} \\
406 {\tt 011:} & {\tt Z=0}\ and {\tt B=1} \\
407 {\tt 100:} & Unused \\
408 {\tt 101:} & {\tt Z=1}\ \\
409 {\tt 110:} & {\tt Z=0}\ \\
410 {\tt 111:} & always \\
415 \subsection{The Hatch}
417 What follows is a conservative approximation of the actual behavior of
419 For complete details on the behavior of the hatch, see
420 \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50}.
422 For the purposes of this section, instructions will be
423 classified into three categories: one-shot instructions ({\tt OS=1}),
424 requeueable instructions ({\tt OS=0}), and {\tt tail} instructions.
426 To avoid deadlock, the programmer must ensure that:
430 \item A requeueable instruction is never followed immediately by a
433 \item A one-shot instruction is never followed immediately by a {\tt
436 \item No contiguous sequence of requeueable instructions is longer
437 than the length of the instruction fifo.
439 \item If a requeueable instruction is preceded by a one-shot
440 instruction or a {\tt tail}, then it must be the case that
441 {\tt Z=0} both before and after the first
442 time that instruction executes.
444 \item If {\tt Z=1}, only a one-shot instruction may set it to a
449 The dock guarantees that:
453 \item If a requeueable instruction is preceded by a one-shot
454 instruction or a {\tt tail}, then the {\it following}
455 instruction will not execute until a {\tt tail} has reached the
458 \item Once a {\tt tail} instruction reaches the hatch, no further
459 instructions will be enqueued until a requeueable instruction
460 reaches the execution stage and {\tt Z=1}.
468 When an instruction arrives on deck, two concurrent processes are
473 \item If the instruction on deck is a requeueable instruction
474 ({\tt OS=0}) and {\tt Z=0}, a copy of
475 the instruction is requeued.
481 If the instruction's predicate condition is not met (see
482 section on predicates), do nothing.
485 {\it Otherwise} if the instruction is interruptible ({\tt I=0})
486 and a torpedo is present in the waiting area: consume the
487 torpedo, set the {\tt Z} flag and
488 set the inner loop counter to one ({\tt ILC=1}).
491 {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it
492 not} a {\tt move}: execute the instruction.
501 \section{Instructions}
503 The dock supports four instructions:
504 {\tt move} (variants: {\tt moveto}, {\tt dispatch}),
511 \subsection{{\tt move}}
513 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
515 \begin{bytefield}{26}
516 \bitheader[b]{14-20}\\
530 \begin{bytefield}{26}
531 \bitheader[b]{0,12,13}\\
532 \bitbox[1]{11}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
535 \bitbox{13}{\tt Immediate}
538 \begin{bytefield}{26}
539 \bitheader[b]{11,12,13}\\
540 \bitbox[1]{11}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:25]\to Path}})\ \ }
549 \begin{bytefield}{26}
550 \bitheader[b]{11,12,13}\\
551 \bitbox[1]{11}{\raggedleft {\tt move} ({\tt Path} unchanged):}
562 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
563 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
564 \item {\tt Dc} - Data Capture: pulse the data latch.
565 \item {\tt Do} - Data Output: fill the data successor.
566 \item {\tt To} - Token Output: fill the token successor.
569 The data successor and token successor must both be empty in order for
570 a {\tt move} instruction to attempt execution.
572 Every time the {\tt move} instruction executes, the {\tt C} flag may
576 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
577 of the incoming packet if {\tt Di} or {\tt Ti} is set.
579 \item At an {\it output} dock the {\tt C} flag is set to a value
580 provided by the ship if the {\tt Di} bit is set, and to the
581 signal bit of the incoming packet if {\tt Di} is clear and {\tt
585 The {\tt flush} instruction is a variant of {\tt move} which is valid
586 only at input docks. It has the same effect as {\tt deliver}, except
587 that it sets a special ``flushing'' indicator along with the data
590 \newcommand{\bitsFlush}{\setlength{\bitwidth}{5mm}
592 \begin{bytefield}{26}
593 \bitheader[b]{14-18}\\
594 \bitbox[r]{7}{\raggedleft{\tt flush}}
606 When a ship fires, it must examine the ``flushing'' indicators on the
607 input docks whose fullness was part of the firing condition. If all
608 of the input docks' flushing indicators are set, the ship must drain
609 all of their data successors and take no action. If some, but not
610 all, of the indicators are set, the ship must drain {\it only the data
611 successors of the docks whose indicators were {\bf not} set}, and
612 take no action. If none of the flushing indicators was set, the ship
619 \subsection{{\tt set}}
621 The {\tt set} command is used to set or decrement the inner loop
622 counter, outer loop counter, and data latch.
624 \newcommand{\bitsSet}{
625 \setlength{\bitwidth}{5mm}
627 \begin{bytefield}{26}
628 \bitheader[b]{19-25}\\
638 \begin{bytefield}{26}
639 \bitheader[b]{0,5,12-18}\\
640 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}}
642 \bitbox{4}{\tt 1000\color{black}}
645 \bitbox{6}{\tt Immediate}
648 \begin{bytefield}{26}
649 \bitheader[b]{12-18}\\
650 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}}
652 \bitbox{4}{\tt 1000\color{black}}
657 \begin{bytefield}{26}
658 \bitheader[b]{12-18}\\
659 \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}}
661 \bitbox{4}{\tt 1000\color{black}}
666 \begin{bytefield}{26}
667 \bitheader[b]{0,5,6,12-18}\\
668 \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}}
670 \bitbox{4}{\tt 0100\color{black}}
674 \bitbox{6}{\tt Immediate}
677 \begin{bytefield}{26}
678 \bitheader[b]{6,12-18}\\
679 \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}}
681 \bitbox{4}{\tt 0100\color{black}}
688 \begin{bytefield}{26}
689 \bitheader[b]{12-18}\\
690 \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}}
692 \bitbox{4}{\tt 0100\color{black}}
697 \begin{bytefield}{26}
698 \bitheader[b]{0,13-18}\\
699 \bitbox[1]{6}{\raggedleft \footnotesize {\tt Sign-Extended Immediate}\to{\tt Data Latch}}
701 \bitbox{4}{\tt 0010\color{black}}
702 \bitbox{1}{\begin{minipage}{0.5cm}{
709 \bitbox{14}{\tt Immediate}
712 \begin{bytefield}{26}
713 \bitheader[b]{0,5,6,11,15-18}\\
714 \bitbox[1]{6}{\raggedleft {\tt Update Flags}}
716 \bitbox{4}{\tt 0001\color{black}}
718 \bitbox{6}{\tt nextA}
719 \bitbox{6}{\tt nextB}
728 The FleetTwo implementation is likely to have an unarchitected
729 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
730 with the possibly-extended literal {\it at the time that the {\tt set}
731 instruction comes on deck}. This latch is then copied into the data
732 latch when a {\tt set Data Latch} instruction
736 The {\tt Sign-Extended Immediate} instruction copies the {\tt
737 Immediate} field into the least significant bits of the data latch.
738 All other bits of the data latch are filled with a copy of the
739 bit marked ``{\tt Sign}.''
742 Each of the {\tt nextA} and {\tt nextB} fields has the following
743 structure, and indicates which old flag values should be logically
744 {\tt OR}ed together to produce the new flag value:
750 \bitbox{1}{${\text{\tt A}}$}
751 \bitbox{1}{$\overline{\text{\tt A}}$}
752 \bitbox{1}{${\text{\tt B}}$}
753 \bitbox{1}{$\overline{\text{\tt B}}$}
754 \bitbox{1}{${\text{{\tt C}\ }}$}
755 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
759 Each bit corresponds to one possible input; all inputs whose bits are
760 set are {\tt OR}ed together, and the resulting value is assigned to
761 the flag. Note that if none of the bits are set, the value assigned
762 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
763 OR}ing any flag with its complement, and that {\tt set Flags} can
764 be used to create a {\tt nop} (no-op) by setting each flag to itself.
770 \subsection{{\tt shift}}
772 \newcommand{\shiftImmediateSize}{19}
774 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
775 bits. When a {\tt shift} instruction is executed, this immediate is copied
776 into the least significant \shiftImmediateSize\ bits of the data latch,
777 and the remaining most significant bits of the data latch are loaded
778 with the value formerly in the least significant bits of the data latch.
779 In this manner, large literals can be built up by ``shifting'' them
780 into the data latch \shiftImmediateSize\ bits at a time.
782 \newcommand{\bitsShift}{
783 \setlength{\bitwidth}{5mm}
785 \begin{bytefield}{26}
786 \bitheader[b]{0,18-20}\\
793 \bitbox{\shiftImmediateSize}{Immediate}
798 The FleetTwo implementation is likely to have an unarchitected
799 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
800 with the literal {\it at the time that the {\tt shift} instruction
801 comes on deck}. This latch is then copied into the data latch when
802 the instruction executes.
806 \subsection{{\tt tail}}
808 \newcommand{\bitsTail}{
809 \setlength{\bitwidth}{5mm}
811 \begin{bytefield}{26}
812 \bitheader[b]{19-20}\\
823 When a {\tt tail} instruction reaches the hatch and the hatch is open,
824 it seals the hatch. The {\tt tail} instruction does not enter the
829 %\subsection{{\tt takeOuterLoopCounter}}
831 %\setlength{\bitwidth}{5mm}
833 %\begin{bytefield}{26}
834 % \bitheader[b]{16-19,21}\\
848 %This instruction copies the value in the outer loop counter {\tt OLC}
849 %into the least significant bits of the data latch and leaves all other
850 %bits of the data latch unchanged.
852 %\subsection{{\tt takeInnerLoopCounter}}
854 %\setlength{\bitwidth}{5mm}
856 %\begin{bytefield}{26}
857 % \bitheader[b]{16-19,21}\\
871 %This instruction copies the value in the inner loop counter {\tt ILC}
872 %into the least significant bits of the data latch and leaves all other
873 %bits of the data latch unchanged.
878 %%\subsection{{\tt interrupt}}
880 %%\setlength{\bitwidth}{5mm}
882 %\begin{bytefield}{26}
883 % \bitheader[b]{0,5,16-19,21}\\
894 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
895 %there for the {\tt OD} stage to be full with an instruction that has
896 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
897 %{\it will not execute}, but {\it may reloop} if the conditions for
899 %\footnote{The ability to interrupt an instruction yet have it reloop is very
900 %useful for processing chunks of data with a fixed size header and/or
901 %footer and a variable length body.}
904 %\subsection{{\tt massacre}}
906 %\setlength{\bitwidth}{5mm}
908 %\begin{bytefield}{26}
909 % \bitheader[b]{16-19,21}\\
921 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
922 %for the {\tt OD} stage to be full with an instruction that has the
923 %{\tt IM} bit set. When this occurs, all instructions in the
924 %instruction fifo (including {\tt OD}) are retired.
926 %\subsection{{\tt clog}}
928 %\setlength{\bitwidth}{5mm}
930 %\begin{bytefield}{26}
931 % \bitheader[b]{16-19,21}\\
943 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
944 %no more instructions will be executed until an {\tt unclog} is
947 %\subsection{{\tt unclog}}
949 %\setlength{\bitwidth}{5mm}
951 %\begin{bytefield}{26}
952 % \bitheader[b]{16-19,21}\\
958 % \bitbox[lrtb]{2}{11}
964 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
965 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
966 %instructions retire.
968 %Note that issuing an {\tt unclog} instruction to a dock which is not
969 %clogged and whose instruction fifo contains no {\tt clog} instructions
970 %will cause the dock to deadlock.
975 \section*{Instruction Encoding Map\color{black}}
977 \hspace{-1cm}{\tt shift}\\
980 \hspace{-1cm}{\tt set}\\
983 \hspace{-1cm}{\tt move}\\
988 \hspace{-1cm}{\tt tail}\\
995 \epsfig{file=all,height=5in,angle=90}
998 \subsection*{Input Dock}
999 \epsfig{file=in,width=8in,angle=90}
1002 \subsection*{Output Dock}
1003 \epsfig{file=out,width=8in,angle=90}
1007 %\epsfig{file=ports,height=5in,angle=90}
1010 %\epsfig{file=best,height=5in,angle=90}