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55 \title{\vspace{-1cm}AM33: The FleetTwo Dock
71 & \color{red} Removed the explicit ``decrement loop counter'' instruction \\
72 & \color{red} Renamed {\tt D}-flag to {\tt Z}-flag \\
75 & \color{red} Moved the {\tt P} (predicate) field to the MSB end of the word \\
76 & \color{red} Changed to a single counter, full word width \\
77 & \color{red} Included one extra Marina erratum I had forgotten \\
78 & \color{red} Changed encoding of {\tt flush} to match internal encoding\\
81 & Added errata for Kessel counter on Marina test chip \\
83 & Added errata for Marina test chip \\
85 & Clarified setting of the {\tt C}-flag\color{black}\\
86 & Removed {\tt OS} bit\color{black}\\
87 & Changed instruction length from 26 bits to 25\color{black}\\
88 & Updated which bits are used when the {\tt Path} latch captures from the data predecessor\color{black}\\
90 & Fixed a one-word typo \\
92 & Added {\tt head} instruction \\
93 & Lengthened external encoding of {\tt tail} instruction by one bit \\
94 & Added {\tt abort} instruction \\
95 & Removed {\tt OS} field from instructions \\
96 & Renamed the {\tt Z}-flag (olc {\bf Z}ero) to the {\tt D}-flag (loop {\bf D}one)\\
98 & Updated diagram in section 3 to put dispatch path near MSB\\
99 & Changed DP[37:25] to DP[37:27]\\
100 & Added note on page 4 regarding previous\\
102 & Roll back ``Distinguish {\tt Z}-flag from OLC=0'' \\
103 & Clarify what ``{\tt X-Extended}'' means \\
104 & Change C-bit source selector from {\tt Di} to {\tt Dc} \\
106 & Distinguish {\tt Z}-flag from OLC=0\\
107 & Add {\tt flush} instruction\\
108 & Change {\t I} bit from ``Interruptable'' to ``Immune''\\
110 & Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\
112 & Note that decision to requeue is based on value of OLC {\it before} execution\\
113 & Note that decision to open the hatch is based on value of {\tt OS} bit\\
115 %& Added {\tt OLC=0} predicate \\
116 %& Eliminated {\tt TAPL} (made possible by previous change) \\
117 %& Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\
119 %& Fixed a few typos \\
120 %& Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\
121 %& Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\
123 %& When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\
124 %& Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\
126 %& Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\
127 %& Reworked encoding of {\tt set} instruction \\
130 %& Factored in Russell Kao's comments (thanks!)\\
131 %& Added mechanism for setting C-flag from fabric even on outboxes\\
133 %& Made {\tt OLC} test a predicate-controlled condition\\
134 %& Rewrote ``on deck'' section \\
135 %& Added ``{\tt unset}'' value for {\tt ILC}\\
136 %& Changed {\tt DP} to {\tt DataPredecessor} for clarity\\
139 %& added comment about address-to-path ship \\
140 %& changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\
141 %& changed the order of instructions in the encoding map \\
143 %& added epilogue fifo to diagrams \\
144 %& indicated that a token sent to the instruction port is treated as a torpedo \\
146 %& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\
147 %& replaced {\tt literal} with {\tt shift} instruction \\
149 %& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\
150 %& Removed ability to manually set the {\tt C} flag \\
151 %& Expanded predicate field to three bits \\
152 %& New literals scheme (via shifting) \\
153 %& Instruction encoding changes made at Ivan's request (for layout purposes) \\
154 %& Added summary of instruction encodings on last page \\
156 %& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\
158 %& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\
159 %& update table 3.1.2 \\
160 %& rename {\tt S} flag to {\tt C} \\
161 %& noted that {\tt setFlags} can be used as {\tt nop} \\
163 %& removed the {\tt L} flag (epilogues can now do this) \\
164 %& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\
165 %& renamed {\tt data} instruction to {\tt literal} \\
166 %& renamed {\tt send} instruction to {\tt move} \\
168 %& added ``if its predicate is true'' to repeat count \\
169 %& added note that red wires do not contact ships \\
170 %& changed name of {\tt flags} instruction to {\tt setFlags} \\
171 %& removed black dot from diagrams \\
172 %& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\
173 %& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\
174 %& indicated that only {\tt send} instructions which wait for data are torpedoable \\
175 %& added section ``Torpedo Details'' \\
176 %& removed {\tt torpedo} instruction \\
179 %& renamed loop+repeat to outer+inner (not in red) \\
180 %& renamed {\tt Z} flag to {\tt L} flag (not in red) \\
181 %& rewrote ``inner and outer loops'' section \\
182 %& updated all diagrams \\
185 %& Moved address bits to the LSB-side of a 37-bit instruction \\
186 %& Added {\it micro-instruction} and {\it composite instruction} terms \\
187 %& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\
188 %& Created the {\tt Hold} field \\
189 %& Changed how ReLooping works \\
190 %& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\
197 \epsfig{file=all,height=1.5in}
198 \epsfig{file=overview-new,height=1.5in}
203 \section{Overview of Fleet}
205 A Fleet processor is organized around a {\it switch fabric}, which is
206 a packet-switched network with reliable in-order delivery. The switch
207 fabric is used to carry data between different functional units,
208 called {\it ships}. Each ship is connected to the switch fabric by
209 one or more programmable elements known as {\it docks}.
211 A {\it path} specifies a route through the switch fabric from a
212 particular {\it source} to a particular {\it destination}. The
213 combination of a path and a single word to be delivered is called a
214 {\it packet}. The switch fabric carries packets from their sources to
215 their destinations. Each dock has \color{red}four\color{black}\
216 destinations: one each for {\it instructions}, \color{red}{\it
217 torpedoes}, {\it tokens},\color{black}\ and {\it words}. A Fleet is
218 programmed by depositing instruction packets into the switch fabric
219 with paths that will lead them to instruction destinations of the
220 docks at which they are to execute.
222 When a packet arrives at the instruction destination of a dock, it is
223 enqueued for execution. Before the instruction executes, it may cause
224 the dock to wait for a packet to arrive at the dock's data destination
225 or for a value to be presented by the ship. When an instruction
226 executes it may consume this data and may present a data value to the
227 ship or transmit a packet.
229 Packets sent to token and torpedo destinations carry no payload. Such
230 packets consume less energy than instruction packets or word packets.
234 \epsfig{file=overview-new,width=2.5in}\\
235 {\it Overview of a Fleet processor; dark gray shading represents the
236 switch fabric, ships are shown in light gray, and docks are shown in blue.}
242 \section{The FleetTwo Dock}
244 The diagram below represents a conceptual view of the interface
245 between ships and the switch fabric; actual implementation circuitry
249 \epsfig{file=all,width=3.5in}\\
250 {\it An ``input'' dock and ``output'' dock connected to a ship. Solid
251 blue lines carry either tokens or data words, red lines carry either
252 instructions or torpedoes, and dashed lines carry only tokens.}
255 Each dock consists of a {\it data latch}, which is as wide as a single
256 machine word and a circular {\it instruction fifo} of
257 instruction-width latches. The values in the instruction fifo control
258 the data latch. The dock also includes a {\it path latch}, which
259 stores the path along which outgoing packets will be
262 Note that the instruction fifo in each dock has a destination of its
263 own; this is the {\it instruction destination} mentioned in the
264 previous section. A token sent to an instruction destination is
265 called a {\it torpedo}; it does not enter the instruction fifo, but
266 rather is held in a waiting area where it may interrupt certain
267 instructions (see the section on the {\tt move} instruction for further
270 From any source to any dock's data destination there are
271 two distinct paths which differ by a single bit. This bit is known as
272 the ``signal'' bit, and the routing of a packet is not affected by it;
273 the signal bit is used to pass control values between docks. Note that paths
274 terminating at an {\it instruction} destination need not have a signal
278 Source-sequence guarantee. Shared across instruction/torpedo (?) and
279 token/word destinations.
283 \section{Instructions}
285 In order to cause an instruction to execute, the programmer must first
286 arrange for that instruction word to arrive in the data latch of some
287 output dock. For example, this might be the ``data read'' output dock
288 of the memory access ship or the output of a fifo ship. Once an
289 instruction has arrived at this output dock, it is {\it dispatched} by
290 sending it to the {\it instruction destination} of the dock at which
293 Each instruction is 25\color{black}\ bits long, which makes
294 it possible for an instruction and an 12\color{black}-bit
295 path to fit in a single word of memory. This path is the path from
296 the {\it dispatching} dock to the {\it executing} dock.
300 \setlength{\bitwidth}{3.5mm}
302 \begin{bytefield}{37}
303 \bitheader[b]{0,24,25,36}\\
304 \bitbox{12}{dispatch path}
305 \bitbox{25}{instruction}
309 Note that the 12\color{black}\ bit {\tt dispatch path}
310 field is not the same width as the 13 bit {\tt Immediate} path field
311 in the {\tt move} instruction, which in turn may not be the same width
312 as the actual path latches in the switch fabric.
314 The algorithm for expanding a path to a wider width is specific to the
315 switch fabric implementation, and is not specified by this
316 document.\footnote{for the Marina experiment, the correct
317 algorithm is to sign-extend the path; the most significant bit of
318 the given path is used to fill the vacant bit of the latch} In
319 particular, because the {\tt dispatch path} field is always used to
320 specify a path which terminates at an instruction destination (never a
321 data destination), and because instruction destinations ignore the
322 signal bit, certain optimizations may be possible.
324 %\subsection{Life Cycle of an Instruction}
326 %The diagram below shows an input dock for purposes of illustration:
329 %\epsfig{file=in,width=4in}\\
336 %\epsfig{file=out,width=4in}\\
337 %{\it an output dock}
340 %\subsection{Format of an Instruction}
342 %All instruction words have the following format:
346 %The {\tt P} bits are a {\it predicate}; this holds a code which
347 %indicates if the instruction should be executed or ignored depending
348 %on the state of flags in the dock. Note that {\tt head} and {\tt
349 %tail} instructions do not have {\tt P} fields.
352 \subsection{Loop Counter}
354 A programmer can perform two types of loops: {\it inner} loops
355 consisting of only one {\tt move} instruction and {\it outer} loops of
356 multiple instructions of any type. Inner loops may be nested within
357 an outer loop, but no other nesting of loops is allowed.
359 The dock has \color{red}one loop counter, called {\tt LC}. It is the
360 same width as a word carried through the switch fabric (37 bits).
366 The dock has four flags: {\tt A}, {\tt B},
367 {\tt C}, and \color{red}{\tt Z}\color{black}.
370 \item The {\tt A} and {\tt B} flags are general-purpose flags which
371 may be set and cleared by the programmer.
375 % The {\tt L} flag, known as the {\it last} flag, is set whenever
376 % the value in the outer counter ({\tt OLC}) is one,
379 % that the dock is in the midst of the last iteration of an
380 % outer loop. This flag can be used to perform certain
381 % operations (such as sending a completion token) only on the last
382 % iteration of an outer loop.
384 \item The {\tt C} flag is known as the {\it control} flag, and may be
385 set by the {\tt move} instruction based on information from the
386 ship or from an inbound packet. See the {\tt move} instruction
389 \item The \color{red}{\tt Z}\color{black}\ flag is known as the
390 \color{red}{\it zero}\color{black}\ flag. The \color{red}{\tt
391 Z}\color{black}\ flag is {\it set} whenever the {\tt LC} is zero.
392 In an actual implementation the \color{red}{\tt Z}\color{black}\
393 flag might require an actual latch; it might simply be derived
394 from the ``zeroness'' of the {\tt LC}.\color{black}
398 \subsection{Predication}
400 All instructions except for {\tt head} and {\tt tail} have a three-bit
401 field marked {\tt P}, which specifies a {\it predicate}.
404 \setlength{\bitwidth}{5mm}
406 \begin{bytefield}{25}
407 \bitheader[b]{0,21,22,24}\\
414 The predicate determines which conditions must be true in order for
415 the instruction to execute; if it is not executed, it is simply {\it
416 ignored}. The table below shows what conditions must be true in
417 order for an instruction to execute:
420 \begin{tabular}{|r|l|}\hline
421 Code & Execute if \\\hline
422 {\tt 000:} & {\tt Z=0}\ and {\tt A=0} \\
423 {\tt 001:} & {\tt Z=0}\ and {\tt A=1} \\
424 {\tt 010:} & {\tt Z=0}\ and {\tt B=0} \\
425 {\tt 011:} & {\tt Z=0}\ and {\tt B=1} \\
426 {\tt 100:} & Unused \\
427 {\tt 101:} & {\tt Z=1}\ \\
428 {\tt 110:} & {\tt Z=0}\ \\
429 {\tt 111:} & always \\
435 \begin{wrapfigure}{r}{40mm}
437 \epsfig{file=requeue,height=1.5in}\\
439 \caption{{\it the requeue stage}}
442 \subsection{The Requeue Stage}
444 The requeue stage has two inputs, which will be referred to as the
445 {\it enqueueing} input and the {\it recirculating} input. It has a
446 single output which feeds into the instruction fifo.
448 The requeue stage has two states: {\sc Updating} and {\sc
451 \subsubsection{The {\sc Updating} State}
453 On initialization, the dock is in the {\sc Updating} state. In this
454 state the requeue stage is performing three tasks:
456 \item it is draining the
457 previous loop's instructions (if any) from the fifo
458 \item it is executing any ``one
459 shot'' instructions which come between the previous loop's {\tt tail}
460 and the next loop's {\tt head}
461 \item it is loading the instructions of
462 the next loop into the fifo.
465 In the {\sc Updating} state, the requeue stage will accept any
466 instruction other than a {\tt tail} which arrives at its {\it
467 enqueueing} input, and pass this instruction to its output. Any
468 instruction other than a {\tt head} which arrives at the {\it
469 recirculating} input will be discarded.
471 Note that when a {\tt tail} instruction arrives at the {\it
472 enqueueing} input, it ``gets stuck'' there. Likewise, when a {\tt
473 head} instruction arrives at the {\it recirculating} input, it also
474 ``gets stuck''. When the requeue stage finds {\it both} a {\tt tail}
475 instruction stuck at the {\it enqueueing} input and a {\tt head}
476 instruction stuck at the {\it recirculating} input, the requeue stage
477 discards both the {\tt head} and {\tt tail} and transitions to the
478 {\sc Circulating} state.
480 \subsubsection{The {\sc Circulating} State}
482 In the {\sc Circulating} state, the dock repeatedly executes the set
483 of instructions that are in the instruction fifo.
485 In the {\sc Circulating} state, the requeue stage will not accept
486 items from its {\it enqueueing} input. Any item presented at the {\it
487 recirculating} input will be passed through to the requeue stage's
490 When an {\tt abort} instruction is executed, the requeue stage
491 transitions back to the {\sc Updating} state. Note that {\tt abort}
492 instructions include a predicate; an {\tt abort} instruction whose
493 predicate is not met will not cause this transition.
499 \section{Instructions}
501 %The dock supports four instructions:
502 %{\tt move} (variants: {\tt moveto}, {\tt dispatch}),
509 \subsection{{\tt move}}
511 \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm}
513 \begin{bytefield}{25}
514 \bitheader[b]{14-21}\\
531 \begin{bytefield}{25}
532 \bitheader[b]{0,12,13}\\
533 \bitbox[1]{10}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})}
536 \bitbox{13}{\tt Immediate}
539 \begin{bytefield}{25}
540 \bitheader[b]{11,12,13}\\
541 \bitbox[1]{10}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:26\color{black}]\to Path}})\ \ }
550 \begin{bytefield}{25}
551 \bitheader[b]{11,12,13}\\
552 \bitbox[1]{10}{\raggedleft {\tt move} ({\tt Path} unchanged):}
567 \item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it.
568 \item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it.
569 \item {\tt Dc} - Data Capture: pulse the data latch.
570 \item {\tt Do} - Data Output: fill the data successor.
571 \item {\tt To} - Token Output: fill the token successor.
574 The data successor and token successor must both be empty in order for
575 a {\tt move} instruction to attempt execution.
578 If the {\tt S} bit is set (not shown -- there is no space left!), the
579 {\tt move} instruction will subtract one from the {\tt LC} counter
580 each time it executes.
581 NOTE: the flavor of {\tt set} instruction which decrements the counter
582 is now unnecessary; we can simply use a ``do-nothing {\tt move}'' with
583 the {\tt S}-bit set for that.
585 If the {\tt R} bit is set, the {\tt move} instruction will execute
586 repeatedly until its predicate no longer holds (or a torpedo strikes).
587 An ``infinite'' or ``standing'' move can be achieved by setting the
588 {\tt R} bit and clearing the {\tt S} bit.
591 \subsection*{Torpedoes}
593 The {\tt I} bit stands for {\tt Immune}, and indicates if the
594 instruction is immune to torpedoes. If a {\tt move} instruction which
595 is not immune is waiting to execute and a torpedo is lying in wait,
596 the torpedo {\it strikes}. \color{red}When a torpedo strikes, the
597 {\tt move} instruction and the torpedo are both consumed and the {\tt
598 LC} is set to zero.\color{black}
600 \subsection*{The C Flag}
602 Every time the {\tt move} instruction executes, the {\tt C} flag may
606 \item At an {\it input} dock the {\tt C} flag is set to the signal bit
607 of the incoming packet.
609 \item At an {\it output} dock the {\tt C} flag is set to a value
610 provided by the ship if the {\tt Dc} bit is set. If the {\tt
611 Dc} bit is not set, the {\tt C} flag is set to the signal bit of
616 \subsection*{Flushing}
618 The {\tt flush} instruction is a variant of {\tt move} which is valid
619 only at input docks. It has the same effect as {\tt deliver}, except
620 that it sets a special ``flushing'' indicator along with the data
623 \newcommand{\bitsFlush}{\setlength{\bitwidth}{5mm}
625 \begin{bytefield}{25}
626 \bitheader[b]{14-18}\\
627 \bitbox[r]{6}{\raggedleft{\tt flush\ \ }}
642 When a ship fires, it must examine the ``flushing'' indicators on the
643 input docks whose fullness was part of the firing condition. If all
644 of the input docks' flushing indicators are set, the ship must drain
645 all of their data successors and take no action. If some, but not
646 all, of the indicators are set, the ship must drain {\it only the data
647 successors of the docks whose indicators were {\bf not} set}, and
648 take no action. If none of the flushing indicators was set, the ship
655 \subsection{{\tt set}}
657 The {\tt set} command is used to set the data latch, the flags, or the
660 \newcommand{\bitsSet}{
662 \begin{bytefield}{25}
663 \bitheader[b]{19-21}\\
679 \begin{bytefield}{25}
680 \bitheader[b]{0,11-18}\\
681 \bitbox[1]{5}{\raggedleft {\tt Immediate}\to{\tt LC}}
683 \bitbox{4}{\tt 1000\color{black}}
686 \bitbox{12}{\tt Immediate}
690 \begin{bytefield}{25}
691 \bitheader[b]{12-18}\\
692 \bitbox[1]{5}{\raggedleft {\tt Data Latch}\to{\tt LC}}
694 \bitbox{4}{\tt 1000\color{black}}
699 \begin{bytefield}{25}
700 \bitheader[b]{0,13-18}\\
701 \bitbox[1]{5}{\raggedleft \footnotesize {\tt Sign-Extended Immediate}\to{\tt Data Latch}}
703 \bitbox{4}{\tt 0010\color{black}}
704 \bitbox{1}{\begin{minipage}{0.5cm}{
711 \bitbox{14}{\tt Immediate}
714 \begin{bytefield}{25}
715 \bitheader[b]{0,5,6,11,15-18}\\
716 \bitbox[1]{5}{\raggedleft {\tt Update Flags}}
718 \bitbox{4}{\tt 0001\color{black}}
720 \bitbox{6}{\tt nextA}
721 \bitbox{6}{\tt nextB}
727 The FleetTwo implementation is likely to have an unarchitected
728 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
729 with the possibly-extended literal {\it at the time that the {\tt set}
730 instruction comes on deck}. This latch is then copied into the data
731 latch when a {\tt set Data Latch} instruction
734 The {\tt Sign-Extended Immediate} instruction copies the {\tt
735 Immediate} field into the least significant bits of the data latch.
736 All other bits of the data latch are filled with a copy of the
737 bit marked ``{\tt Sign}.''
740 Each of the {\tt nextA} and {\tt nextB} fields has the following
741 structure, and indicates which old flag values should be logically
742 {\tt OR}ed together to produce the new flag value:
748 \bitbox{1}{${\text{\tt A}}$}
749 \bitbox{1}{$\overline{\text{\tt A}}$}
750 \bitbox{1}{${\text{\tt B}}$}
751 \bitbox{1}{$\overline{\text{\tt B}}$}
752 \bitbox{1}{${\text{{\tt C}\ }}$}
753 \bitbox{1}{$\overline{\text{{\tt C}\ }}$}
757 Each bit corresponds to one possible input; all inputs whose bits are
758 set are {\tt OR}ed together, and the resulting value is assigned to
759 the flag. Note that if none of the bits are set, the value assigned
760 is zero. Note also that it is possible to produce a {\tt 1} by {\tt
761 OR}ing any flag with its complement, and that {\tt set Flags} can
762 be used to create a {\tt nop} (no-op) by setting each flag to itself.
768 \subsection{{\tt shift}}
770 \newcommand{\shiftImmediateSize}{19}
772 Each {\tt shift} instruction carries an immediate of \shiftImmediateSize\
773 bits. When a {\tt shift} instruction is executed, this immediate is copied
774 into the least significant \shiftImmediateSize\ bits of the data latch,
775 and the remaining most significant bits of the data latch are loaded
776 with the value formerly in the least significant bits of the data latch.
777 In this manner, large literals can be built up by ``shifting'' them
778 into the data latch \shiftImmediateSize\ bits at a time.
780 \newcommand{\bitsShift}{
781 \setlength{\bitwidth}{5mm}
783 \begin{bytefield}{25}
784 \bitheader[b]{0,18-21}\\
793 \bitbox{\shiftImmediateSize}{Immediate}
798 The FleetTwo implementation is likely to have an unarchitected
799 ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded
800 with the literal {\it at the time that the {\tt shift} instruction
801 comes on deck}. This latch is then copied into the data latch when
802 the instruction executes.
806 \subsection{{\tt abort}}
807 \newcommand{\bitsAbort}{\setlength{\bitwidth}{5mm}
809 \begin{bytefield}{25}
810 \bitheader[b]{18-21}\\
825 An {\tt abort} instruction causes a loop to exit; see the section on
826 the Requeue Stage for further details.
828 \subsection{{\tt head}}
829 \newcommand{\bitsHead}{
830 \setlength{\bitwidth}{5mm}
832 \begin{bytefield}{25}
833 \bitheader[b]{18-21}\\
848 A {\tt head} instruction marks the start of a loop; see the section on
849 the Requeue Stage for further details.
852 \subsection{{\tt tail}}
853 \newcommand{\bitsTail}{
854 \setlength{\bitwidth}{5mm}
856 \begin{bytefield}{25}
857 \bitheader[b]{18-21}\\
872 A {\tt tail} instruction marks the end of a loop; see the section on
873 the Requeue Stage for further details.
877 %\subsection{{\tt takeOuterLoopCounter}}
879 %\setlength{\bitwidth}{5mm}
881 %\begin{bytefield}{25}
882 % \bitheader[b]{16-19,21}\\
896 %This instruction copies the value in the outer loop counter {\tt OLC}
897 %into the least significant bits of the data latch and leaves all other
898 %bits of the data latch unchanged.
900 %\subsection{{\tt takeInnerLoopCounter}}
902 %\setlength{\bitwidth}{5mm}
904 %\begin{bytefield}{25}
905 % \bitheader[b]{16-19,21}\\
919 %This instruction copies the value in the inner loop counter {\tt ILC}
920 %into the least significant bits of the data latch and leaves all other
921 %bits of the data latch unchanged.
926 %%\subsection{{\tt interrupt}}
928 %%\setlength{\bitwidth}{5mm}
930 %\begin{bytefield}{25}
931 % \bitheader[b]{0,5,16-19,21}\\
942 %When an {\tt interrupt} instruction reaches {\tt IH}, it will wait
943 %there for the {\tt OD} stage to be full with an instruction that has
944 %the {\tt IM} bit set. When this occurs, the instruction at {\tt OD}
945 %{\it will not execute}, but {\it may reloop} if the conditions for
947 %\footnote{The ability to interrupt an instruction yet have it reloop is very
948 %useful for processing chunks of data with a fixed size header and/or
949 %footer and a variable length body.}
952 %\subsection{{\tt massacre}}
954 %\setlength{\bitwidth}{5mm}
956 %\begin{bytefield}{25}
957 % \bitheader[b]{16-19,21}\\
969 %When a {\tt massacre} instruction reaches {\tt IH}, it will wait there
970 %for the {\tt OD} stage to be full with an instruction that has the
971 %{\tt IM} bit set. When this occurs, all instructions in the
972 %instruction fifo (including {\tt OD}) are retired.
974 %\subsection{{\tt clog}}
976 %\setlength{\bitwidth}{5mm}
978 %\begin{bytefield}{25}
979 % \bitheader[b]{16-19,21}\\
991 %When a {\tt clog} instruction reaches {\tt OD}, it remains there and
992 %no more instructions will be executed until an {\tt unclog} is
995 %\subsection{{\tt unclog}}
997 %\setlength{\bitwidth}{5mm}
999 %\begin{bytefield}{25}
1000 % \bitheader[b]{16-19,21}\\
1006 % \bitbox[lrtb]{2}{11}
1008 % \bitbox[tbr]{16}{}
1012 %When an {\tt unclog} instruction reaches {\tt IH}, it will wait there
1013 %until a {\tt clog} instruction is at {\tt OD}. When this occurs, both
1014 %instructions retire.
1016 %Note that issuing an {\tt unclog} instruction to a dock which is not
1017 %clogged and whose instruction fifo contains no {\tt clog} instructions
1018 %will cause the dock to deadlock.
1021 \section*{Marina Errata}
1023 The following additional restrictions have been imposed on the dock in
1024 the Marina test chip:
1026 \subsection*{All Versions}
1031 A Marina dock initializes with the {\tt ILC}, {\tt OLC}, and flags in
1032 an indeterminate state.
1035 The instruction immediately after a {\tt move} instruction must not be
1036 a {\tt set flags} instruction which utilizes the {\tt C}-flag (the
1037 value of the {\tt C}-flag is not stable for a brief time after a {\tt
1043 If a {\tt move} instruction is torpedoable (ie it has the {\tt I} bit
1044 set to {\tt 0}), it {\it must} have either the {\tt Ti} bit or {\tt
1045 Di} bit set (or both). It is not permitted for a torpedoable {\tt
1046 move} to have both bits cleared.
1053 \subsection*{Marina with Ivan's Counter}
1059 A torpedoable {\tt move} instruction must not be followed immediately
1060 by a {\tt set olc} instruction or another torpedoable {\tt move}.
1064 This document specifies that when a torpedoable {\tt move} instruction
1065 executes successfully, the \color{red}{\tt Z}\color{black} flag is unchanged. In Marina, when
1066 a torpedoable {\tt move} instruction executes successfully, it causes
1067 the \color{red}{\tt Z}\color{black} flag to be set if the {\tt OLC} was zero and causes it to
1068 be cleared if the {\tt OLC} was nonzero. Thus, in the following
1069 instruction sequence:
1074 send token to self:i;
1076 [*] send token to self;
1082 Will leave the \color{red}{\tt Z}\color{black} flag {\it set} on Marina, whereas a strict
1083 implementation of this document would leave it cleared.
1085 In practice, this distinction rarely matters.
1089 \subsection*{Marina with Kessels Counter}
1091 With the Kessels counter, the \color{red}{\tt Z}\color{black}-flag {\it is exactly equal to}
1092 the zeroness of the {\tt OLC}; it cannot be ``out of sync'' with it.
1097 Every ``load OLC'' instruction must be predicated on the \color{red}{\tt Z}\color{black}-flag
1098 being {\it set}. This is a sneaky way of forcing the programmer to
1099 ``run down'' the counter before loading it, because Kessels' counter
1100 does not support ``unloading.''
1103 Every ``decrement OLC'' instruction must be predicated on the {\tt
1104 D}-flag being {\it cleared}. This way we never have to check if the
1105 counter is already empty before decrementing.
1108 The instruction after a torpedoable {\tt move} must not be predicated
1109 on the \color{red}{\tt Z}\color{black}-flag being {\it set} (it may be predicated on the {\tt
1110 D}-flag being {\it cleared}. This is because, while the move
1111 instruction is waiting to execute, the \color{red}{\tt Z}\color{black}-flag will be cleared,
1112 and the predicate stage believes that it can skip the instruction even
1113 though {\tt do[ins]} is still high (I think this is dumb).
1121 \section*{Instruction Encoding Map\color{black}}
1124 \vspace{3mm}\hspace{-1cm}{\tt move}\hspace{1cm}\vspace{-6mm}\\
1128 \vspace{3mm}\hspace{-1cm}{\tt shift}\hspace{1cm}\vspace{-6mm}\\
1131 \vspace{3mm}\hspace{-1cm}{\tt set}\hspace{1cm}\vspace{-6mm}\\
1134 \vspace{3mm}\hspace{-1cm}{\tt abort}\hspace{1cm}\vspace{-6mm}\\
1137 \vspace{3mm}\hspace{-1cm}{\tt head}\hspace{1cm}\vspace{-6mm}\\
1140 \vspace{3mm}\hspace{-1cm}{\tt tail}\hspace{1cm}\vspace{-6mm}\\
1145 %\epsfig{file=all,height=5in,angle=90}
1148 %\subsection*{Input Dock}
1149 %\epsfig{file=in,width=8in,angle=90}
1152 %\subsection*{Output Dock}
1153 %\epsfig{file=out,width=8in,angle=90}
1157 %\epsfig{file=ports,height=5in,angle=90}
1160 %\epsfig{file=best,height=5in,angle=90}