chips/marina/electric/marina_padframe.delib/PVDD1CDG_18.sch

   1 Hmarina_padframe|8.09a
   2
   3 # Cell PVDD1CDG_18;1{sch}
   4 CPVDD1CDG_18;1{sch}||schematic|1185175551078|1241276175361|I|ATTR_CDL_template(D5G2;NTX-6.5;Y-52.5;)SX$(node_name) $(POC18) $(VDDPST18) $(VSS) $(VSSPST18) $(VDD) /PVDD1CDG_18|ATTR_NCC(D5G2;NTX-9;Y-43;)S[blackBox Artisan pad layout does not exist properly in electric,joinGroup tpdn90g18:PVDD1CDG_18{lay}]|ATTR_SPICE_netlist_file(D5G2;NTX-8.5;Y-48.5;)Stpdn90g18_3.spi
   5 IPVDD1CDG_18;1{ic}|PVDD1CDG@0||41|20|||D5G4;
   6 Ngeneric:Facet-Center|art@0||0|0||||AV
   7 NOff-Page|conn@0||-10|19|||R|
   8 NOff-Page|conn@1||-30|5||||
   9 NOff-Page|conn@2||10|5||||
  10 NOff-Page|conn@3||-30|-4||||
  11 NOff-Page|conn@4||10|-4||||
  12 NOff-Page|conn@5||-30|-15||||
  13 NOff-Page|conn@6||10|-15||||
  14 NOff-Page|conn@7||-30|-26||||
  15 NOff-Page|conn@8||10|-26||||
  16 NOff-Page|conn@9||-30|-35||||
  17 NOff-Page|conn@10||10|-35||||
  18 NWire_Pin|pin@0||-10|5||||
  19 Ngeneric:Invisible-Pin|pin@2||-9|37.5|||||ART_message(D5G5;)SPVDD1CDG_18
  20 Ngeneric:Invisible-Pin|pin@3||-9|30|||||ART_message(D5G3;)Score (1V) power pin
  21 Awire|net@0|||0|pin@0||-10|5|conn@1|y|-28|5
  22 Awire|net@1|||0|conn@2|a|8|5|pin@0||-10|5
  23 Awire|net@2|||900|conn@0|a|-10|17|pin@0||-10|5
  24 Awire|net@3|||0|conn@4|a|8|-4|conn@3|y|-28|-4
  25 Awire|net@4|||0|conn@6|a|8|-15|conn@5|y|-28|-15
  26 Awire|net@7|||0|conn@10|a|8|-35|conn@9|y|-28|-35
  27 Awire|net@8|||1800|conn@7|y|-28|-26|conn@8|a|8|-26
  28 EPOC18||D5G2;|conn@5|a|B
  29 EPOC18_11|POC18_1|D5G2;|conn@6|y|B
  30 Evdd_2|VDD|D5G2;|conn@1|a|P
  31 EVDD_4|VDDPST18|D5G2;|conn@7|a|P
  32 EVDD_5|VDDPST18_1|D5G2;|conn@8|y|P
  33 Evdd_3|VDD_1|D5G2;|conn@2|y|P
  34 Evdd|VDD_2|D5G2;|conn@0|y|P
  35 Evss_2|VSS|D5G2;|conn@3|a|G
  36 EVSS_4|VSSPST18|D5G2;|conn@9|a|G
  37 EVSS_5|VSSPST18_1|D5G2;|conn@10|y|G
  38 Evss_3|VSS_1|D5G2;|conn@4|y|G
  39 X