chips/marina/electric/marina_padframe.delib/PVDD2POC_18.sch

   1 Hmarina_padframe|8.09a
   2
   3 # Cell PVDD2POC_18;1{sch}
   4 CPVDD2POC_18;1{sch}||schematic|1185175551078|1241283030309|I|ATTR_CDL_template(D5G2;NTX-7.5;Y-50.5;)SX$(node_name) $(POC18) $(VDDPST18) $(VSS) $(VSSPST18) $(VDD) /PVDD2POC_18|ATTR_NCC(D5G2;NTX-9;Y-43.5;)S[blackBox Artisan pad layout does not exist properly in electric,joinGroup tpdn90g18:PVDD2POC_18{lay}]|ATTR_SPICE_netlist_file(D5G2;NTX-8.5;Y-47.5;)Stpdn90g18_3.spi
   5 IPVDD2POC_18;1{ic}|PVDD2CDG@0||37|11|||D5G4;
   6 Ngeneric:Facet-Center|art@0||0|0||||AV
   7 NOff-Page|conn@1||-30|5||||
   8 NOff-Page|conn@2||10|5||||
   9 NOff-Page|conn@3||-30|-4||||
  10 NOff-Page|conn@4||10|-4||||
  11 NOff-Page|conn@5||-30|-15||||
  12 NOff-Page|conn@6||10|-15||||
  13 NOff-Page|conn@7||-30|-26||||
  14 NOff-Page|conn@8||10|-26||||
  15 NOff-Page|conn@9||-30|-35||||
  16 NOff-Page|conn@10||10|-35||||
  17 Ngeneric:Invisible-Pin|pin@2||-9.5|18|||||ART_message(D5G3;)S[I/O (1.8V) power pin including,power-on circuit (POC),replace one VDD2CDG pin,with VDD2POC]
  18 Ngeneric:Invisible-Pin|pin@3||-9.5|28.5|||||ART_message(D5G5;)SPVDD2POC_18
  19 Awire|net@3|||0|conn@4|a|8|-4|conn@3|y|-28|-4
  20 Awire|net@4|||0|conn@6|a|8|-15|conn@5|y|-28|-15
  21 Awire|net@7|||0|conn@10|a|8|-35|conn@9|y|-28|-35
  22 Awire|net@8|||1800|conn@1|y|-28|5|conn@2|a|8|5
  23 Awire|net@9|||1800|conn@7|y|-28|-26|conn@8|a|8|-26
  24 EPOC18||D5G2;|conn@5|a|B
  25 EPOC18_1||D5G2;|conn@6|y|B
  26 EVDD||D5G2;|conn@1|a|P
  27 EVDDPST18||D5G2;|conn@7|a|P
  28 EVDDPST18_1||D5G2;|conn@8|y|P
  29 EVDD_1||D5G2;|conn@2|y|P
  30 EVSS||D5G2;|conn@3|a|G
  31 EVSSPST18||D5G2;|conn@9|a|G
  32 EVSSPST18_1||D5G2;|conn@10|y|G
  33 EVSS_1||D5G2;|conn@4|y|G
  34 X