chips/marina/electric/marina_padframe.delib/config_input.sch

   1 Hmarina_padframe|8.09k
   2
   3 # Cell config_input;1{sch}
   4 Cconfig_input;1{sch}||schematic|1185253248982|1243982549452|I
   5 ITIEHI;1{ic}|TIEHI@0||-35|36.5|||D5G4;
   6 ITIEHI;1{ic}|TIEHI@1||-42|36.5|||D5G4;
   7 ITIELO;1{ic}|TIELO@0||-21|36.5|||D5G4;
   8 ITIELO;1{ic}|TIELO@1||-14|36.5|||D5G4;
   9 ITIELO;1{ic}|TIELO@2||-28|36.5|||D5G4;
  10 ITIELO;1{ic}|TIELO@3||-56|36.5|||D5G4;
  11 Ngeneric:Facet-Center|art@0||0|0||||AV
  12 Iconfig_input;1{ic}|config_i@0||-4.5|46|||D5G4;
  13 NOff-Page|conn@0||-49|25|||YRRR|
  14 NOff-Page|conn@1||-35|25|||RRR|
  15 NOff-Page|conn@2||-28|25|||RRR|
  16 NOff-Page|conn@3||-21|25|||RRR|
  17 NOff-Page|conn@4||-14|25|||RRR|
  18 NOff-Page|conn@5||-42|25|||RRR|
  19 NOff-Page|conn@6||-49|39|||YRRR|
  20 NOff-Page|conn@7||-56|25|||RRR|
  21 Ngeneric:Invisible-Pin|pin@0||-28|20|||||ART_message(D5G1;)S8mA drive
  22 Ngeneric:Invisible-Pin|pin@1||-17.5|20|||||ART_message(D5G1;)Sno pull up/down
  23 Ngeneric:Invisible-Pin|pin@2||-38.5|20|||||ART_message(D5G1;)Sinput pad
  24 Awire|net@13|||2700|conn@3|a|-21|27|TIELO@0|Y|-21|32.5
  25 Awire|net@16|||900|TIELO@2|Y|-28|32.5|conn@2|a|-28|27
  26 Awire|net@19|||2700|conn@1|a|-35|27|TIEHI@0|Y|-35|32.5
  27 Awire|net@21|||2700|conn@5|a|-42|27|TIEHI@1|Y|-42|32.5
  28 Awire|net@22|||2700|conn@4|a|-14|27|TIELO@1|Y|-14|32.5
  29 Awire|net@23|||2700|conn@0|y|-49|27|conn@6|a|-49|37
  30 Awire|net@24|||900|TIELO@3|Y|-56|32.5|conn@7|a|-56|27
  31 EC||D5G2;|conn@0|a|I
  32 EI_2|DS|D5G2;|conn@2|y|O
  33 EDS_1|I|D5G2;|conn@7|y|O
  34 EPE_1|IE|D5G2;|conn@5|y|O
  35 EI_1|OEN|D5G2;|conn@1|y|O
  36 EI_4|PE|D5G2;|conn@4|y|O
  37 EI_3|PS|D5G2;|conn@3|y|O
  38 Edata||D5G2;|conn@6|y|O
  39 X