chips/marina/electric/marina_padframe.delib/config_output.sch

   1 Hmarina_padframe|8.09j
   2
   3 # Cell config_output;1{sch}
   4 Cconfig_output;1{sch}||schematic|1185253248982|1241481713009|I
   5 ITIELO;1{ic}|TIELO@0||-28|36|||D5G4;
   6 ITIELO;1{ic}|TIELO@1||-35|36|||D5G4;
   7 ITIELO;1{ic}|TIELO@2||-42|36|||D5G4;
   8 ITIELO;1{ic}|TIELO@3||-21|36|||D5G4;
   9 ITIELO;1{ic}|TIELO@4||-14|36|||D5G4;
  10 Ngeneric:Facet-Center|art@0||0|0||||AV
  11 Iconfig_output;1{ic}|config_o@0||-7|47|||D5G4;
  12 NOff-Page|conn@0||-49|39|||RRR|
  13 NOff-Page|conn@1||-35|25|||RRR|
  14 NOff-Page|conn@2||-28|25|||RRR|
  15 NOff-Page|conn@3||-21|25|||RRR|
  16 NOff-Page|conn@4||-14|25|||RRR|
  17 NOff-Page|conn@5||-42|25|||RRR|
  18 NOff-Page|conn@6||-49|25|||RRR|
  19 Ngeneric:Invisible-Pin|pin@7||-28|20.5|||||ART_message(D5G1;)S8mA drive
  20 Ngeneric:Invisible-Pin|pin@8||-17.5|20.5|||||ART_message(D5G1;)Sno pull up/down
  21 Ngeneric:Invisible-Pin|pin@9||-38|20.5|||||ART_message(D5G1;)Soutput pad
  22 Awire|net@16|||2700|conn@2|a|-28|27|TIELO@0|Y|-28|32
  23 Awire|net@21|||2700|conn@5|a|-42|27|TIELO@2|Y|-42|32
  24 Awire|net@22|||2700|conn@1|a|-35|27|TIELO@1|Y|-35|32
  25 Awire|net@23|||2700|conn@4|a|-14|27|TIELO@4|Y|-14|32
  26 Awire|net@24|||2700|conn@3|a|-21|27|TIELO@3|Y|-21|32
  27 Awire|net@25|||2700|conn@6|a|-49|27|conn@0|y|-49|37
  28 EDS||D5G2;|conn@2|y|O
  29 EI||D5G2;|conn@6|y|O
  30 EIE||D5G2;|conn@5|y|O
  31 EOEN||D5G2;|conn@1|y|O
  32 EPE||D5G2;|conn@4|y|O
  33 EPS||D5G2;|conn@3|y|O
  34 Edata@97761025|data|D5G2;|conn@0|a|I
  35 X