add results from actual silicon in marina/results/
[fleet.git] / marina / electric / marina_padframe.delib / PVSS3CDG_18.sch
1 Hmarina_padframe|8.09a
2
3 # Cell PVSS3CDG_18;1{sch}
4 CPVSS3CDG_18;1{sch}||schematic|1185175551078|1241276204972|I|ATTR_CDL_template(D5G2;NTX-9.5;Y-52.5;)SX$(node_name) $(POC18) $(VDDPST18) $(VSS) $(VDD) /PVSS3CDG_18|ATTR_NCC(D5G2;NTX-9.5;Y-45;)S[blackBox Artisan pad layout does not exist properly in electric,joinGroup tpdn90g18:PVSS3CDG_18{lay}]|ATTR_SPICE_netlist_file(D5G2;NTX-9.5;Y-49.5;)Stpdn90g18_3.spi
5 IPVSS3CDG_18;1{ic}|PVDD1CDG@0||41|20|||D5G4;
6 Ngeneric:Facet-Center|art@0||0|0||||AV
7 NOff-Page|conn@0||-10|19|||R|
8 NOff-Page|conn@1||-30|5||||
9 NOff-Page|conn@2||10|5||||
10 NOff-Page|conn@3||-30|-4||||
11 NOff-Page|conn@4||10|-4||||
12 NOff-Page|conn@5||-30|-15||||
13 NOff-Page|conn@6||10|-15||||
14 NOff-Page|conn@7||-30|-26||||
15 NOff-Page|conn@8||10|-26||||
16 NOff-Page|conn@9||-30|-35||||
17 NOff-Page|conn@10||10|-35||||
18 NWire_Pin|pin@2||-10|-4||||
19 NWire_Pin|pin@3||-10|-35||||
20 Ngeneric:Invisible-Pin|pin@4||-10|41.5|||||ART_message(D5G5;)SPVSS3CDG_18
21 Ngeneric:Invisible-Pin|pin@5||-10|34|||||ART_message(D5G3;)Scommon ground pin (shared VSS and VSSPST18)
22 Awire|net@3|||0|pin@2||-10|-4|conn@3|y|-28|-4
23 Awire|net@4|||0|conn@6|a|8|-15|conn@5|y|-28|-15
24 Awire|net@7|||0|pin@3||-10|-35|conn@9|y|-28|-35
25 Awire|net@8|||1800|conn@1|y|-28|5|conn@2|a|8|5
26 Awire|net@9|||0|conn@4|a|8|-4|pin@2||-10|-4
27 Awire|net@10|||900|conn@0|a|-10|17|pin@2||-10|-4
28 Awire|net@11|||0|conn@10|a|8|-35|pin@3||-10|-35
29 Awire|net@12|||900|pin@2||-10|-4|pin@3||-10|-35
30 Awire|net@13|||1800|conn@7|y|-28|-26|conn@8|a|8|-26
31 EPOC18||D5G2;|conn@5|a|B
32 EPOC18_1||D5G2;|conn@6|y|B
33 EVDD||D5G2;|conn@1|a|P
34 EVDDPST18||D5G2;|conn@7|a|P
35 EVDDPST18_1||D5G2;|conn@8|y|P
36 EVDD_1||D5G2;|conn@2|y|P
37 EVSS||D5G2;|conn@3|a|G
38 EVSSPST18||D5G2;|conn@9|a|G
39 EVSSPST18_1||D5G2;|conn@10|y|G
40 EVSS_1||D5G2;|conn@4|y|G
41 EVDD_2|VSS_2|D5G2;|conn@0|y|G
42 X