ships/DDR2.ship

   1 ship: DDR2
   2
   3 == Ports ===========================================================
   4 data  in:    inAddrRead
   5 data  in:    inAddrWrite
   6 data  in:    inDataWrite
   7
   8 data  out:   out
   9
  10 percolate down:  clk200_p      1
  11
  12 percolate inout: ddr2_dq       64
  13 percolate inout: ddr2_dqs      8
  14 percolate inout: ddr2_dqs_n    8
  15 percolate up:    ddr2_a        13
  16 percolate up:    ddr2_ba       2
  17 percolate up:    ddr2_ras_n    1
  18 percolate up:    ddr2_cas_n    1
  19 percolate up:    ddr2_we_n     1
  20 percolate up:    ddr2_cs_n     1
  21 percolate up:    ddr2_odt      1
  22 percolate up:    ddr2_cke      1
  23 percolate up:    ddr2_dm       8
  24 percolate up:    ddr2_ck       2
  25 percolate up:    ddr2_ck_n     2
  26
  27 == TeX ==============================================================
  28
  29 == Fleeterpreter ====================================================
  30     public void service() { }
  31 == FleetSim ==============================================================
  32
  33 == FPGA ==============================================================
  34
  35 // clocking //////////////////////////////////////////////////////////////////////////////
  36
  37 wire clk0;
  38 wire clkdiv0;
  39 wire clk0_unbuffered;
  40 wire clkdiv0_unbuffered;
  41 wire dcm_lock;
  42
  43 BUFG clk200_p_buf (.I(clk200_p),            .O(clk200_p_buffered));
  44 BUFG clk0_fb_buf  (.I(clk0_unbuffered),     .O(clk0_fb));
  45 BUFG clk0_fb_buf2 (.I(clk0_unbuffered),     .O(clk0));
  46 BUFG clkdiv0_bufg (.I(clkdiv0_unbuffered),  .O(clkdiv0));
  47
  48 DCM
  49  #(
  50    .CLKIN_PERIOD          (10.0),
  51    .DLL_FREQUENCY_MODE    ("LOW"),
  52    .DUTY_CYCLE_CORRECTION ("TRUE"),
  53    .CLKDV_DIVIDE          (2),
  54    .FACTORY_JF            (16'hF0F0)
  55   ) ddr2_dcm (
  56     .CLKIN     (clk),
  57     .CLKFB     (clk0_fb),
  58     .CLKDV     (clkdiv0_unbuffered),
  59     .CLK0      (clk0_unbuffered),
  60     .CLK90     (clk90),
  61     .LOCKED    (dcm_lock),
  62     .RST       (rst)
  63   );
  64
  65 // controller instance ////////////////////////////////////////////////////////////////////////
  66
  67 wire        phy_init_done;
  68 wire        app_wdf_afull;
  69 wire        app_af_afull;
  70 reg         app_wdf_wren;
  71 reg  [63:0] app_wdf_data;
  72 reg         app_af_wren;
  73 reg  [2:0]  app_af_cmd;
  74 reg  [30:0] app_af_addr;
  75 wire        rd_data_valid;
  76 wire [63:0] rd_data_fifo_out;
  77
  78 reg         read_waiting;
  79 reg  [7:0]  mask;
  80 reg  [6:0]  burst_count;
  81
  82 ddr2_sdram # (
  83     .BANK_WIDTH(2),                    // # of memory bank addr bits.
  84     .CKE_WIDTH(1),                     // # of memory clock enable outputs.
  85     .CLK_WIDTH(2),                     // # of clock outputs.
  86     .COL_WIDTH(10),                    // # of memory column bits.
  87     .CS_NUM(1),                        // # of separate memory chip selects.
  88     .CS_WIDTH(1),                      // # of total memory chip selects.
  89     .CS_BITS(0),                       // set to log2(CS_NUM) (rounded up).
  90     .DM_WIDTH(8),                      // # of data mask bits.
  91     .DQ_WIDTH(64),                     // # of data width.
  92     .DQ_PER_DQS(8),                    // # of DQ data bits per strobe.
  93     .DQS_WIDTH(8),                     // # of DQS strobes.
  94     .DQ_BITS(6),                       // set to log2(DQS_WIDTH*DQ_PER_DQS).
  95     .DQS_BITS(3),                      // set to log2(DQS_WIDTH).
  96     .ODT_WIDTH(1),                     // # of memory on-die term enables.
  97     .ROW_WIDTH(13),                    // # of memory row and # of addr bits.
  98     .ADDITIVE_LAT(0),                  // additive write latency.
  99     .BURST_LEN(4),                     // burst length (in double words).
 100     .BURST_TYPE(0),                    // burst type (=0 seq; =1 interleaved).
 101     .CAS_LAT(3),                       // CAS latency.
 102     .ECC_ENABLE(0),                    // enable ECC (=1 enable).
 103     .APPDATA_WIDTH(128),               // # of usr read/write data bus bits.
 104     .MULTI_BANK_EN(1),                 // Keeps multiple banks open. (= 1 enable).
 105     .TWO_T_TIME_EN(1),                 // 2t timing for unbuffered dimms.
 106     .ODT_TYPE(1),                      // ODT (=0(none),=1(75),=2(150),=3(50)).
 107     .REDUCE_DRV(0),                    // reduced strength mem I/O (=1 yes).
 108     .REG_ENABLE(0),                    // registered addr/ctrl (=1 yes).
 109     .TREFI_NS(7800),                   // auto refresh interval (ns).
 110     .TRAS(40000),                      // active->precharge delay.
 111     .TRCD(15000),                      // active->read/write delay.
 112     .TRFC(105000),                     // refresh->refresh, refresh->active delay.
 113     .TRP(15000),                       // precharge->command delay.
 114     .TRTP(7500),                       // read->precharge delay.
 115     .TWR(15000),                       // used to determine write->precharge.
 116     .TWTR(7500),                       // write->read delay.
 117     .HIGH_PERFORMANCE_MODE("TRUE"),    // # = TRUE, the IODELAY performance mode is set to high.
 118                                        // # = FALSE, the IODELAY performance mode is set to low.
 119     .SIM_ONLY(0),                      // = 1 to skip SDRAM power up delay.
 120     .DEBUG_EN(0),                      // Enable debug signals/controls.
 121                                        // When this parameter is changed from 0 to 1,
 122                                        // make sure to uncomment the coregen commands
 123                                        // in ise_flow.bat or create_ise.bat files in
 124                                        // par folder.
 125     .CLK_PERIOD(10000),                // Core/Memory clock period (in ps).
 126     .DQS_IO_COL(16'b0000000000000000), // I/O column location of DQS groups
 127                                        // (=0, left; =1 center, =2 right).
 128     .DQ_IO_MS(64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100),
 129                                        // Master/Slave location of DQ I/O (=0 slave).
 130     .RST_ACT_LOW(1)                    // =1 for active low reset, =0 for active high.
 131 ) ddr2_sdram (
 132     .sys_rst_n                 (!rst),
 133
 134     .ddr2_dq                   (ddr2_dq),
 135     .ddr2_a                    (ddr2_a),
 136     .ddr2_ba                   (ddr2_ba),
 137     .ddr2_ras_n                (ddr2_ras_n),
 138     .ddr2_cas_n                (ddr2_cas_n),
 139     .ddr2_we_n                 (ddr2_we_n),
 140     .ddr2_cs_n                 (ddr2_cs_n),
 141     .ddr2_odt                  (ddr2_odt),
 142     .ddr2_cke                  (ddr2_cke),
 143     .ddr2_dm                   (ddr2_dm),
 144     .ddr2_dqs                  (ddr2_dqs),
 145     .ddr2_dqs_n                (ddr2_dqs_n),
 146     .ddr2_ck                   (ddr2_ck),
 147     .ddr2_ck_n                 (ddr2_ck_n),
 148
 149     .phy_init_done             (phy_init_done),
 150
 151     .app_wdf_afull             (app_wdf_afull),
 152     .app_af_afull              (app_af_afull),
 153     .rd_data_valid             (rd_data_valid),
 154     .rd_data_fifo_out          (rd_data_fifo_out),
 155
 156     .app_wdf_wren              ((~phy_init_done) ? 0 : app_wdf_wren),
 157     .app_wdf_data              ((~phy_init_done) ? 0 : app_wdf_data),
 158     .app_wdf_mask_data         ((~phy_init_done) ? 0 : mask),
 159
 160     .app_af_wren               ((~phy_init_done) ? 0 : app_af_wren),
 161     .app_af_cmd                (app_af_cmd),
 162     .app_af_addr               (app_af_addr),
 163
 164     .dcm_lock                  (dcm_lock),
 165     .clk0                      (clk0),
 166     .clk90                     (clk90),
 167     .clkdiv0                   (clkdiv0),
 168
 169     .clk200                    (clk200_p_buffered)
 170   );
 171
 172 // custom code //////////////////////////////////////////////////////////////////////////////
 173
 174 reg  [37:0] out_d;
 175 assign out_d_ = out_d;
 176
 177 // grossly inefficient -- always uses only the first word of a burst!
 178 always @(posedge clk) begin
 179   if (rst) begin
 180     `reset
 181     app_wdf_wren <= 0;
 182     app_af_wren  <= 0;
 183     read_waiting <= 0;
 184     burst_count  <= 0;
 185
 186   end else begin
 187     `cleanup
 188
 189     mask <= 8'b11111111;
 190     if (burst_count == 0 || burst_count == 1) begin
 191       app_wdf_wren <= 0;
 192       app_af_wren  <= 0;
 193     end else if ((burst_count > 1) && (app_af_cmd == 3'b000)) begin
 194       app_af_wren  <= ~burst_count[0];
 195     end
 196
 197     if (burst_count > 0) begin
 198       burst_count <= burst_count - 1;
 199     end else if ((~read_waiting) && rd_data_valid) begin
 200       /* wait */
 201     end else if (read_waiting) begin
 202       if (rd_data_valid) begin
 203         read_waiting <= 0;
 204         out_d <= { 1'b0, rd_data_fifo_out[36:0] };
 205         `fill_out
 206       end
 207     end else if (app_wdf_afull || app_af_afull) begin
 208       /* wait */
 209     end else if (`inAddrWrite_full && `inDataWrite_full && `out_empty) begin
 210       `drain_inDataWrite
 211       `drain_inAddrWrite
 212       app_wdf_data   <= inDataWrite_d;
 213       app_af_addr    <= { inAddrWrite_d, 2'b00 };
 214       app_af_cmd     <= 3'b000;
 215       app_af_wren    <= 1;
 216       app_wdf_wren   <= 1;
 217       burst_count    <= 7;
 218       out_d          <= { 1'b1, 37'b0 };
 219       mask           <= 8'b00000000;
 220       `fill_out
 221     end else if (`inAddrRead_full && `out_empty) begin
 222       `drain_inAddrRead
 223       app_af_addr    <= { inAddrRead_d, 2'b00 };
 224       app_af_cmd     <= 3'b001;
 225       app_af_wren    <= 1;
 226       burst_count    <= 3;
 227       read_waiting   <= 1;
 228     end
 229   end
 230 end
 231
 232 == UCF ==============================================================
 233
 234 Net clk200_p PERIOD =  5 ns HIGH 50%;  # 200Mhz
 235
 236 #NET "*/u_ddr2_infrastructure/sys_clk_ibufg" TNM_NET =  "SYS_CLK";
 237 Net "ddr2_0/clk0" TNM_NET = "SYS_CLK";
 238 TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 10 ns HIGH 50 %;
 239
 240 #NET "*/u_ddr2_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
 241 Net clk200_p TNM_NET = "SYS_CLK_200";
 242 TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;
 243
 244 # suggested by
 245 # http://www.xilinx.com/support/answers/31606.htm
 246 # NET "clk_0" TNM_NET = "SYS_clk_0";
 247 # TIMESPEC "TS_SYS_clk_0" = PERIOD "SYS_clk_0" 5 ns HIGH 50 %;
 248 # NET "clk_90" TNM_NET = "SYS_clk_90";
 249 # TIMESPEC "TS_SYS_clk_90" = PERIOD "SYS_clk_90" "TS_SYS_clk_0" PHASE 1.25 ns HIGH 50 %;
 250
 251 ################################################################################
 252 # I/O STANDARDS
 253 ################################################################################
 254
 255 NET  "ddr2_dq[*]"                               IOSTANDARD = SSTL18_II_DCI;
 256 NET  "ddr2_a[*]"                                IOSTANDARD = SSTL18_II;
 257 NET  "ddr2_ba[*]"                               IOSTANDARD = SSTL18_II;
 258 NET  "ddr2_ras_n"                               IOSTANDARD = SSTL18_II;
 259 NET  "ddr2_cas_n"                               IOSTANDARD = SSTL18_II;
 260 NET  "ddr2_we_n"                                IOSTANDARD = SSTL18_II;
 261 NET  "ddr2_cs_n"                             IOSTANDARD = SSTL18_II;
 262 NET  "ddr2_odt"                              IOSTANDARD = SSTL18_II;
 263 NET  "ddr2_cke"                              IOSTANDARD = SSTL18_II;
 264 NET  "ddr2_dm[*]"                               IOSTANDARD = SSTL18_II;
 265 #NET  "sys_clk_p"                                IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
 266 #NET  "sys_clk_n"                                IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
 267 #NET  "clk200_p"                                 IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
 268 #NET  "clk200_n"                                 IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
 269 #NET  "sys_rst_n"                                IOSTANDARD = LVCMOS18;
 270 #NET  "phy_init_done"                           IOSTANDARD = LVCMOS18;
 271 #NET  "error"                                   IOSTANDARD = LVCMOS18;
 272 NET  "ddr2_dqs[*]"                              IOSTANDARD = DIFF_SSTL18_II_DCI;
 273 NET  "ddr2_dqs_n[*]"                            IOSTANDARD = DIFF_SSTL18_II_DCI;
 274 NET  "ddr2_ck[*]"                               IOSTANDARD = DIFF_SSTL18_II;
 275 NET  "ddr2_ck_n[*]"                             IOSTANDARD = DIFF_SSTL18_II;
 276
 277 ################################################################################
 278 # Location Constraints
 279 ################################################################################
 280
 281 NET  "ddr2_dq[0]"                                LOC = "AF30" ;       #Bank 17
 282 NET  "ddr2_dq[1]"                                LOC = "AK31" ;       #Bank 17
 283 NET  "ddr2_dq[2]"                                LOC = "AF31" ;       #Bank 17
 284 NET  "ddr2_dq[3]"                                LOC = "AD30" ;       #Bank 17
 285 NET  "ddr2_dq[4]"                                LOC = "AJ30" ;       #Bank 17
 286 NET  "ddr2_dq[5]"                                LOC = "AF29" ;       #Bank 17
 287 NET  "ddr2_dq[6]"                                LOC = "AD29" ;       #Bank 17
 288 NET  "ddr2_dq[7]"                                LOC = "AE29" ;       #Bank 17
 289 NET  "ddr2_dq[8]"                                LOC = "AH27" ;       #Bank 21
 290 NET  "ddr2_dq[9]"                                LOC = "AF28" ;       #Bank 21
 291 NET  "ddr2_dq[10]"                               LOC = "AH28" ;       #Bank 21
 292 NET  "ddr2_dq[11]"                               LOC = "AA28" ;       #Bank 21
 293 NET  "ddr2_dq[12]"                               LOC = "AG25" ;       #Bank 21
 294 NET  "ddr2_dq[13]"                               LOC = "AJ26" ;       #Bank 21
 295 NET  "ddr2_dq[14]"                               LOC = "AG28" ;       #Bank 21
 296 NET  "ddr2_dq[15]"                               LOC = "AB28" ;       #Bank 21
 297 NET  "ddr2_dq[16]"                               LOC = "AC28" ;       #Bank 21
 298 NET  "ddr2_dq[17]"                               LOC = "AB25" ;       #Bank 21
 299 NET  "ddr2_dq[18]"                               LOC = "AC27" ;       #Bank 21
 300 NET  "ddr2_dq[19]"                               LOC = "AA26" ;       #Bank 21
 301 NET  "ddr2_dq[20]"                               LOC = "AB26" ;       #Bank 21
 302 NET  "ddr2_dq[21]"                               LOC = "AA24" ;       #Bank 21
 303 NET  "ddr2_dq[22]"                               LOC = "AB27" ;       #Bank 21
 304 NET  "ddr2_dq[23]"                               LOC = "AA25" ;       #Bank 21
 305 NET  "ddr2_dq[24]"                               LOC = "AC29" ;       #Bank 17
 306 NET  "ddr2_dq[25]"                               LOC = "AB30" ;       #Bank 17
 307 NET  "ddr2_dq[26]"                               LOC = "W31" ;        #Bank 17
 308 NET  "ddr2_dq[27]"                               LOC = "V30" ;        #Bank 17
 309 NET  "ddr2_dq[28]"                               LOC = "AC30" ;       #Bank 17
 310 NET  "ddr2_dq[29]"                               LOC = "W29" ;        #Bank 17
 311 NET  "ddr2_dq[30]"                               LOC = "V27" ;        #Bank 17
 312 NET  "ddr2_dq[31]"                               LOC = "W27" ;        #Bank 17
 313 NET  "ddr2_dq[32]"                               LOC = "V29" ;        #Bank 17
 314 NET  "ddr2_dq[33]"                               LOC = "Y27" ;        #Bank 17
 315 NET  "ddr2_dq[34]"                               LOC = "Y26" ;        #Bank 17
 316 NET  "ddr2_dq[35]"                               LOC = "W24" ;        #Bank 17
 317 NET  "ddr2_dq[36]"                               LOC = "V28" ;        #Bank 17
 318 NET  "ddr2_dq[37]"                               LOC = "W25" ;        #Bank 17
 319 NET  "ddr2_dq[38]"                               LOC = "W26" ;        #Bank 17
 320 NET  "ddr2_dq[39]"                               LOC = "V24" ;        #Bank 17
 321 NET  "ddr2_dq[40]"                               LOC = "R24" ;        #Bank 19
 322 NET  "ddr2_dq[41]"                               LOC = "P25" ;        #Bank 19
 323 NET  "ddr2_dq[42]"                               LOC = "N24" ;        #Bank 19
 324 NET  "ddr2_dq[43]"                               LOC = "P26" ;        #Bank 19
 325 NET  "ddr2_dq[44]"                               LOC = "T24" ;        #Bank 19
 326 NET  "ddr2_dq[45]"                               LOC = "N25" ;        #Bank 19
 327 NET  "ddr2_dq[46]"                               LOC = "P27" ;        #Bank 19
 328 NET  "ddr2_dq[47]"                               LOC = "N28" ;        #Bank 19
 329 NET  "ddr2_dq[48]"                               LOC = "M28" ;        #Bank 19
 330 NET  "ddr2_dq[49]"                               LOC = "L28" ;        #Bank 19
 331 NET  "ddr2_dq[50]"                               LOC = "F25" ;        #Bank 19
 332 NET  "ddr2_dq[51]"                               LOC = "H25" ;        #Bank 19
 333 NET  "ddr2_dq[52]"                               LOC = "K27" ;        #Bank 19
 334 NET  "ddr2_dq[53]"                               LOC = "K28" ;        #Bank 19
 335 NET  "ddr2_dq[54]"                               LOC = "H24" ;        #Bank 19
 336 NET  "ddr2_dq[55]"                               LOC = "G26" ;        #Bank 19
 337 NET  "ddr2_dq[56]"                               LOC = "G25" ;        #Bank 19
 338 NET  "ddr2_dq[57]"                               LOC = "M26" ;        #Bank 19
 339 NET  "ddr2_dq[58]"                               LOC = "J24" ;        #Bank 19
 340 NET  "ddr2_dq[59]"                               LOC = "L26" ;        #Bank 19
 341 NET  "ddr2_dq[60]"                               LOC = "J27" ;        #Bank 19
 342 NET  "ddr2_dq[61]"                               LOC = "M25" ;        #Bank 19
 343 NET  "ddr2_dq[62]"                               LOC = "L25" ;        #Bank 19
 344 NET  "ddr2_dq[63]"                               LOC = "L24" ;        #Bank 19
 345 NET  "ddr2_a[12]"                                LOC = "T31" ;        #Bank 15
 346 NET  "ddr2_a[11]"                                LOC = "R29" ;        #Bank 15
 347 NET  "ddr2_a[10]"                                LOC = "J31" ;        #Bank 15
 348 NET  "ddr2_a[9]"                                 LOC = "R28" ;        #Bank 15
 349 NET  "ddr2_a[8]"                                 LOC = "M31" ;        #Bank 15
 350 NET  "ddr2_a[7]"                                 LOC = "P30" ;        #Bank 15
 351 NET  "ddr2_a[6]"                                 LOC = "P31" ;        #Bank 15
 352 NET  "ddr2_a[5]"                                 LOC = "L31" ;        #Bank 15
 353 NET  "ddr2_a[4]"                                 LOC = "K31" ;        #Bank 15
 354 NET  "ddr2_a[3]"                                 LOC = "P29" ;        #Bank 15
 355 NET  "ddr2_a[2]"                                 LOC = "N29" ;        #Bank 15
 356 NET  "ddr2_a[1]"                                 LOC = "M30" ;        #Bank 15
 357 NET  "ddr2_a[0]"                                 LOC = "L30" ;        #Bank 15
 358 NET  "ddr2_ba[1]"                                LOC = "J30" ;        #Bank 15
 359 NET  "ddr2_ba[0]"                                LOC = "G31" ;        #Bank 15
 360 NET  "ddr2_ras_n"                                LOC = "H30" ;        #Bank 15
 361 NET  "ddr2_cas_n"                                LOC = "E31" ;        #Bank 15
 362 NET  "ddr2_we_n"                                 LOC = "K29" ;        #Bank 15
 363 NET  "ddr2_cs_n"                                 LOC = "L29" ;        #Bank 15
 364 NET  "ddr2_odt"                                  LOC = "F31" ;        #Bank 15
 365 NET  "ddr2_cke"                                  LOC = "T28" ;        #Bank 15
 366 NET  "ddr2_cke[1]"                               LOC = "U30" ;
 367 NET  "ddr2_dm[0]"                                LOC = "AJ31" ;       #Bank 17
 368 NET  "ddr2_dm[1]"                                LOC = "AE28" ;       #Bank 21
 369 NET  "ddr2_dm[2]"                                LOC = "Y24" ;        #Bank 21
 370 NET  "ddr2_dm[3]"                                LOC = "Y31" ;        #Bank 17
 371 NET  "ddr2_dm[4]"                                LOC = "V25" ;        #Bank 17
 372 NET  "ddr2_dm[5]"                                LOC = "P24" ;        #Bank 19
 373 NET  "ddr2_dm[6]"                                LOC = "F26" ;        #Bank 19
 374 NET  "ddr2_dm[7]"                                LOC = "J25" ;        #Bank 19
 375 NET  "sys_clk_p"                                 LOC = "H14" ;        #Bank 3
 376 NET  "sys_clk_n"                                 LOC = "H15" ;        #Bank 3
 377 NET  "clk200_p"                                  LOC = "L19" ;        #Bank 3
 378 NET  "clk200_n"                                  LOC = "K19" ;        #Bank 3
 379 NET  "sys_rst_n"                                 LOC = "E9";            #Bank 20
 380 #NET  "phy_init_done"                             LOC = "H18" ;       #Bank 3
 381 NET  "error"                                     LOC = "F6";            #Bank 12
 382 NET  "ddr2_dqs[0]"                               LOC = "AA29" ;       #Bank 17
 383 NET  "ddr2_dqs_n[0]"                             LOC = "AA30" ;       #Bank 17
 384 NET  "ddr2_dqs[1]"                               LOC = "AK28" ;       #Bank 21
 385 NET  "ddr2_dqs_n[1]"                             LOC = "AK27" ;       #Bank 21
 386 NET  "ddr2_dqs[2]"                               LOC = "AK26" ;       #Bank 21
 387 NET  "ddr2_dqs_n[2]"                             LOC = "AJ27" ;       #Bank 21
 388 NET  "ddr2_dqs[3]"                               LOC = "AB31" ;       #Bank 17
 389 NET  "ddr2_dqs_n[3]"                             LOC = "AA31" ;       #Bank 17
 390 NET  "ddr2_dqs[4]"                               LOC = "Y28" ;        #Bank 17
 391 NET  "ddr2_dqs_n[4]"                             LOC = "Y29" ;        #Bank 17
 392 NET  "ddr2_dqs[5]"                               LOC = "E26" ;        #Bank 19
 393 NET  "ddr2_dqs_n[5]"                             LOC = "E27" ;        #Bank 19
 394 NET  "ddr2_dqs[6]"                               LOC = "H28" ;        #Bank 19
 395 NET  "ddr2_dqs_n[6]"                             LOC = "G28" ;        #Bank 19
 396 NET  "ddr2_dqs[7]"                               LOC = "G27" ;        #Bank 19
 397 NET  "ddr2_dqs_n[7]"                             LOC = "H27" ;        #Bank 19
 398 NET  "ddr2_ck[0]"                                LOC = "AK29" ;       #Bank 21
 399 NET  "ddr2_ck_n[0]"                              LOC = "AJ29" ;       #Bank 21
 400 NET  "ddr2_ck[1]"                                LOC = "E28" ;        #Bank 19
 401 NET  "ddr2_ck_n[1]"                              LOC = "F28" ;        #Bank 19
 402
 403 ################################################################################
 404 #IDELAYCTRL Location Constraints
 405 ################################################################################
 406
 407 INST "*/IDELAYCTRL_INST[0].u_idelayctrl" LOC=IDELAYCTRL_X0Y1;
 408 INST "*/IDELAYCTRL_INST[1].u_idelayctrl" LOC=IDELAYCTRL_X0Y2;
 409 INST "*/IDELAYCTRL_INST[2].u_idelayctrl" LOC=IDELAYCTRL_X0Y6;
 410
 411 ###############################################################################
 412 # Define multicycle paths - these paths may take longer because additional
 413 # time allowed for logic to settle in calibration/initialization FSM
 414 ###############################################################################
 415
 416 # MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
 417 #          multicycle paths from originating flip-flop to ANY destination
 418 #          flip-flop (or in some cases, it can also be a BRAM)
 419 # MUX Select for either rising/falling CLK0 for 2nd stage read capture
 420 INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
 421 TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
 422 "TS_SYS_CLK" * 4;
 423 # MUX select for read data - optional delay on data to account for byte skews
 424 #INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
 425 #TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
 426 #"TS_SYS_CLK" * 4;
 427 # Calibration/Initialization complete status flag (for PHY logic only) - can
 428 # be used to drive both flip-flops and BRAMs
 429 INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
 430 TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
 431 "TS_SYS_CLK" * 4;
 432 TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
 433 "TS_SYS_CLK" * 4;
 434 # Select (address) bits for SRL32 shift registers used in stage3/stage4
 435 # calibration
 436 INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
 437 TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;
 438 #INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
 439 #TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;
 440 INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
 441   TNM = "TNM_CAL_RDEN_DLY";
 442 TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
 443   "TS_SYS_CLK" * 4;
 444
 445 ###############################################################################
 446 # DQS Read Post amble Glitch Squelch circuit related constraints
 447 ###############################################################################
 448
 449 ###############################################################################
 450 # LOC placement of DQS-squelch related IDDR and IDELAY elements
 451 # Each circuit can be located at any of the following locations:
 452 #  1. Unused "N"-side of DQS differential pair I/O
 453 #  2. DM data mask (output only, input side is free for use)
 454 #  3. Any output-only site
 455 ###############################################################################
 456
 457 INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y96";
 458 INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y96";
 459 INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y58";
 460 INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y58";
 461 INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y62";
 462 INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y62";
 463 INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y100";
 464 INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y100";
 465 INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y102";
 466 INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y102";
 467 INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y256";
 468 INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y256";
 469 INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y260";
 470 INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y260";
 471 INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce"  LOC = "ILOGIC_X0Y262";
 472 INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce"  LOC = "IODELAY_X0Y262";
 473
 474 ###############################################################################
 475 # LOC and timing constraints for flop driving DQS CE enable signal
 476 # from fabric logic. Even though the absolute delay on this path is
 477 # calibrated out (when synchronizing this output to DQS), the delay
 478 # should still be kept as low as possible to reduce post-calibration
 479 # voltage/temp variations - these are roughly proportional to the
 480 # absolute delay of the path
 481 ###############################################################################
 482
 483 INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff"  LOC = SLICE_X0Y48;
 484 INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff"  LOC = SLICE_X0Y29;
 485 INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff"  LOC = SLICE_X0Y31;
 486 INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff"  LOC = SLICE_X0Y50;
 487 INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff"  LOC = SLICE_X0Y51;
 488 INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff"  LOC = SLICE_X0Y128;
 489 INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff"  LOC = SLICE_X0Y130;
 490 INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff"  LOC = SLICE_X0Y131;
 491
 492 # Control for DQS gate - from fabric flop. Prevent "runaway" delay -
 493 # two parts to this path: (1) from fabric flop to IDELAY, (2) from
 494 # IDELAY to asynchronous reset of IDDR that drives the DQ CE's
 495 # This can be relaxed by the user for lower frequencies:
 496 # 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
 497 # In general PAR should be able to route this
 498 # within 900ps over all speed grades.
 499 NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
 500 NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
 501
 502 ###############################################################################
 503 # "Half-cycle" path constraint from IDDR to CE pin for all DQ IDDR's
 504 # for DQS Read Post amble Glitch Squelch circuit
 505 ###############################################################################
 506
 507 # Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
 508 #  where slack account for rise-time of DQS on board. For now assume slack =
 509 #  0.400ns (based on initial SPICE simulations, assumes use of ODT), so
 510 #  time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
 511 INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
 512 INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
 513 TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;
 514
 515 ###############################################################################
 516 # MIG 2.2: Prevent unrelated logic from being packed into any slices used
 517 #          by read data capture RPM's - if unrelated logic gets packed into
 518 #          these slices, it could cause the DIRT strings that define the
 519 #          IDDR -> fabric flop routing to become unroutable during PAR stage
 520 #          (unrelated logic may require routing resources required by the
 521 #          DIRT strings - MAP does not currently take into account DIRT
 522 #          strings when placing logic
 523 ###############################################################################
 524
 525 AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
 526
 527 ###############################################################################
 528 # Location constraints for DQ read-data capture flops in fabric (for 2nd
 529 # stage capture)
 530 ###############################################################################
 531
 532 INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y42;            #  AF30      X0Y22    *
 533 INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y43;            #  AK31      X0Y23
 534 INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y45;            #  AF31      X0Y25
 535 INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y46;            #  AD30      X0Y26
 536 INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y41;            #  AJ30      X0Y21
 537 INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y42;            #  AF29      X0Y22    ***
 538 INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y44;            #  AD29      X0Y24
 539 INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y44;            #  AE29      X0Y24
 540 INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y28;            #  AH27      X0Y8     ***
 541 INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y32;            #  AF28      X0Y12
 542 INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y33;           #  AH28      X0Y13
 543 INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y34;           #  AA28      X0Y14
 544 INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y26;           #  AG25      X0Y6
 545 INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y28;           #  AJ26      X0Y8     *
 546 INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y33;           #  AG28      X0Y13
 547 INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y34;           #  AB28      X0Y14
 548 INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y35;           #  AC28      X0Y15
 549 INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y36;           #  AB25      X0Y16    ***
 550 INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y38;           #  AC27      X0Y18
 551 INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y39;           #  AA26      X0Y19
 552 INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y36;           #  AB26      X0Y16    *
 553 INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y37;           #  AA24      X0Y17
 554 INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y38;           #  AB27      X0Y18
 555 INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y39;           #  AA25      X0Y19
 556 INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y46;           #  AC29      X0Y26
 557 INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y49;           #  AB30      X0Y29    ***
 558 INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y53;           #  W31       X0Y33
 559 INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y55;           #  V30       X0Y35
 560 INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y49;           #  AC30      X0Y29    *
 561 INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y52;           #  W29       X0Y32
 562 INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y54;           #  V27       X0Y34    ***
 563 INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y56;           #  W27       X0Y36
 564 INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y52;           #  V29       X0Y32
 565 INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y56;           #  Y27       X0Y36
 566 INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y58;           #  Y26       X0Y38
 567 INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y59;           #  W24       X0Y39
 568 INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y54;           #  V28       X0Y34   *
 569 INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y57;           #  W25       X0Y37
 570 INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y58;           #  W26       X0Y38
 571 INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y59;           #  V24       X0Y39
 572 INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y120;          #  R24       X0Y100
 573 INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y121;          #  P25       X0Y101
 574 INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y122;          #  N24       X0Y102
 575 INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y123;          #  P26       X0Y103
 576 INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y120;          #  T24       X0Y100
 577 INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y121;          #  N25       X0Y101
 578 INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y123;          #  P27       X0Y103
 579 INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y124;          #  N28       X0Y104
 580 INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y124;          #  M28       X0Y104
 581 INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y126;          #  L28       X0Y106
 582 INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y132;          #  F25       X0Y112
 583 INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y133;          #  H25       X0Y113
 584 INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y125;          #  K27       X0Y105
 585 INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y126;          #  K28       X0Y106
 586 INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y133;          #  H24       X0Y113
 587 INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y134;          #  G26       X0Y114
 588 INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y134;          #  G25       X0Y114
 589 INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y136;          #  M26       X0Y116
 590 INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y137;          #  J24       X0Y117
 591 INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y138;          #  L26       X0Y118
 592 INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y135;          #  J27       X0Y115
 593 INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y136;          #  M25       X0Y116
 594 INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y138;          #  L25       X0Y118
 595 INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise"  RLOC_ORIGIN = X0Y139;          #  L24       X0Y119
 596
 597
 598 == Test ==============================================================
 599 #expect 20
 600 #expect 16
 601 #expect 12
 602
 603 #ship debug : Debug
 604 #ship ddr   : DDR2
 605
 606 debug.in:
 607   set ilc=*; recv, deliver;
 608
 609 ddr.out:
 610   set ilc=3; collect;
 611   send token to ddr.inAddrRead;
 612   set ilc=3; collect, send to debug.in;
 613
 614 ddr.inAddrWrite:
 615   set word=  0x1; deliver;
 616   set word= 0x10; deliver;
 617   set word=0x100; deliver;
 618
 619 ddr.inDataWrite:
 620   set word=20; deliver;
 621   set word=16; deliver;
 622   set word=12; deliver;
 623
 624 ddr.inAddrRead:
 625   recv token;
 626   set word=  0x1; deliver;
 627   set word= 0x10; deliver;
 628   set word=0x100; deliver;
 629
 630
 631 == Constants ========================================================
 632
 633 == Contributors =========================================================
 634 Adam Megacz <megacz@cs.berkeley.edu>