Bee2 branch landing: step 1

[fleet.git] / src / edu / berkeley / fleet / fpga / bee2 / async_fifo_8_8_128.edn

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2006 2 18 19 6 14)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 7.1.04i; Cores Update # 3"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2005 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_wr_response_latency = 1 ")
       (comment "c_has_rd_data_count = 1 ")
       (comment "c_din_width = 8 ")
       (comment "c_has_wr_data_count = 1 ")
       (comment "InstanceName = async_fifo_8_8_128 ")
       (comment "c_implementation_type = 2 ")
       (comment "c_family = virtex2p ")
       (comment "c_has_wr_rst = 0 ")
       (comment "c_underflow_low = 0 ")
       (comment "c_has_meminit_file = 0 ")
       (comment "c_has_overflow = 0 ")
       (comment "c_preload_latency = 0 ")
       (comment "c_dout_width = 8 ")
       (comment "c_rd_depth = 128 ")
       (comment "c_default_value = BlankString ")
       (comment "c_mif_file_name = BlankString ")
       (comment "c_has_underflow = 0 ")
       (comment "c_has_rd_rst = 0 ")
       (comment "c_has_almost_full = 0 ")
       (comment "c_has_rst = 1 ")
       (comment "c_data_count_width = 2 ")
       (comment "c_has_wr_ack = 0 ")
       (comment "c_wr_ack_low = 0 ")
       (comment "c_common_clock = 0 ")
       (comment "c_rd_pntr_width = 7 ")
       (comment "c_has_almost_empty = 0 ")
       (comment "c_rd_data_count_width = 8 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_wr_pntr_width = 7 ")
       (comment "c_overflow_low = 0 ")
       (comment "c_prog_empty_type = 0 ")
       (comment "c_optimization_mode = 0 ")
       (comment "c_wr_data_count_width = 8 ")
       (comment "c_preload_regs = 1 ")
       (comment "c_dout_rst_val = 0 ")
       (comment "c_has_data_count = 0 ")
       (comment "c_prog_full_thresh_negate_val = 96 ")
       (comment "c_wr_depth = 128 ")
       (comment "c_prog_empty_thresh_negate_val = 32 ")
       (comment "c_prog_empty_thresh_assert_val = 32 ")
       (comment "c_has_valid = 0 ")
       (comment "c_init_wr_pntr_val = 0 ")
       (comment "c_prog_full_thresh_assert_val = 96 ")
       (comment "c_use_fifo16_flags = 0 ")
       (comment "c_has_backup = 0 ")
       (comment "c_valid_low = 0 ")
       (comment "c_prim_fifo_type = 512 ")
       (comment "c_count_type = 0 ")
       (comment "c_prog_full_type = 0 ")
       (comment "c_memory_type = 1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
   )
   (external async_fifo_8_8_128_fifo_generator_v2_2_xst_1_lib (edifLevel 0)
       (technology (numberDefinition))
       (cell async_fifo_8_8_128_fifo_generator_v2_2_xst_1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port clk (direction INPUT))
                   (port backup (direction INPUT))
                   (port backup_marker (direction INPUT))
                   (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh "prog_empty_thresh<6:0>") 7 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh_assert "prog_empty_thresh_assert<6:0>") 7 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh_negate "prog_empty_thresh_negate<6:0>") 7 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh "prog_full_thresh<6:0>") 7 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh_assert "prog_full_thresh_assert<6:0>") 7 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh_negate "prog_full_thresh_negate<6:0>") 7 ) (direction INPUT))
                   (port rd_clk (direction INPUT))
                   (port rd_en (direction INPUT))
                   (port rd_rst (direction INPUT))
                   (port rst (direction INPUT))
                   (port wr_clk (direction INPUT))
                   (port wr_en (direction INPUT))
                   (port wr_rst (direction INPUT))
                   (port almost_empty (direction OUTPUT))
                   (port almost_full (direction OUTPUT))
                   (port ( array ( rename data_count "data_count<1:0>") 2 ) (direction OUTPUT))
                   (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT))
                   (port empty (direction OUTPUT))
                   (port full (direction OUTPUT))
                   (port overflow (direction OUTPUT))
                   (port prog_empty (direction OUTPUT))
                   (port prog_full (direction OUTPUT))
                   (port valid (direction OUTPUT))
                   (port ( array ( rename rd_data_count "rd_data_count<7:0>") 8 ) (direction OUTPUT))
                   (port underflow (direction OUTPUT))
                   (port wr_ack (direction OUTPUT))
                   (port ( array ( rename wr_data_count "wr_data_count<7:0>") 8 ) (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell async_fifo_8_8_128
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT))
   (port ( rename rd_clk "rd_clk") (direction INPUT))
   (port ( rename rd_en "rd_en") (direction INPUT))
   (port ( rename rst "rst") (direction INPUT))
   (port ( rename wr_clk "wr_clk") (direction INPUT))
   (port ( rename wr_en "wr_en") (direction INPUT))
   (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT))
   (port ( rename empty "empty") (direction OUTPUT))
   (port ( rename full "full") (direction OUTPUT))
   (port ( array ( rename rd_data_count "rd_data_count<7:0>") 8 ) (direction OUTPUT))
   (port ( array ( rename wr_data_count "wr_data_count<7:0>") 8 ) (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU2
      (viewRef view_1 (cellRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1 (libraryRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_lib)))
   )
   (net (rename N5 "din<7>")
    (joined
      (portRef (member din 0))
      (portRef (member din 0) (instanceRef BU2))
    )
   )
   (net (rename N6 "din<6>")
    (joined
      (portRef (member din 1))
      (portRef (member din 1) (instanceRef BU2))
    )
   )
   (net (rename N7 "din<5>")
    (joined
      (portRef (member din 2))
      (portRef (member din 2) (instanceRef BU2))
    )
   )
   (net (rename N8 "din<4>")
    (joined
      (portRef (member din 3))
      (portRef (member din 3) (instanceRef BU2))
    )
   )
   (net (rename N9 "din<3>")
    (joined
      (portRef (member din 4))
      (portRef (member din 4) (instanceRef BU2))
    )
   )
   (net (rename N10 "din<2>")
    (joined
      (portRef (member din 5))
      (portRef (member din 5) (instanceRef BU2))
    )
   )
   (net (rename N11 "din<1>")
    (joined
      (portRef (member din 6))
      (portRef (member din 6) (instanceRef BU2))
    )
   )
   (net (rename N12 "din<0>")
    (joined
      (portRef (member din 7))
      (portRef (member din 7) (instanceRef BU2))
    )
   )
   (net (rename N55 "rd_clk")
    (joined
      (portRef rd_clk)
      (portRef rd_clk (instanceRef BU2))
    )
   )
   (net (rename N56 "rd_en")
    (joined
      (portRef rd_en)
      (portRef rd_en (instanceRef BU2))
    )
   )
   (net (rename N58 "rst")
    (joined
      (portRef rst)
      (portRef rst (instanceRef BU2))
    )
   )
   (net (rename N59 "wr_clk")
    (joined
      (portRef wr_clk)
      (portRef wr_clk (instanceRef BU2))
    )
   )
   (net (rename N60 "wr_en")
    (joined
      (portRef wr_en)
      (portRef wr_en (instanceRef BU2))
    )
   )
   (net (rename N66 "dout<7>")
    (joined
      (portRef (member dout 0))
      (portRef (member dout 0) (instanceRef BU2))
    )
   )
   (net (rename N67 "dout<6>")
    (joined
      (portRef (member dout 1))
      (portRef (member dout 1) (instanceRef BU2))
    )
   )
   (net (rename N68 "dout<5>")
    (joined
      (portRef (member dout 2))
      (portRef (member dout 2) (instanceRef BU2))
    )
   )
   (net (rename N69 "dout<4>")
    (joined
      (portRef (member dout 3))
      (portRef (member dout 3) (instanceRef BU2))
    )
   )
   (net (rename N70 "dout<3>")
    (joined
      (portRef (member dout 4))
      (portRef (member dout 4) (instanceRef BU2))
    )
   )
   (net (rename N71 "dout<2>")
    (joined
      (portRef (member dout 5))
      (portRef (member dout 5) (instanceRef BU2))
    )
   )
   (net (rename N72 "dout<1>")
    (joined
      (portRef (member dout 6))
      (portRef (member dout 6) (instanceRef BU2))
    )
   )
   (net (rename N73 "dout<0>")
    (joined
      (portRef (member dout 7))
      (portRef (member dout 7) (instanceRef BU2))
    )
   )
   (net (rename N74 "empty")
    (joined
      (portRef empty)
      (portRef empty (instanceRef BU2))
    )
   )
   (net (rename N75 "full")
    (joined
      (portRef full)
      (portRef full (instanceRef BU2))
    )
   )
   (net (rename N80 "rd_data_count<7>")
    (joined
      (portRef (member rd_data_count 0))
      (portRef (member rd_data_count 0) (instanceRef BU2))
    )
   )
   (net (rename N81 "rd_data_count<6>")
    (joined
      (portRef (member rd_data_count 1))
      (portRef (member rd_data_count 1) (instanceRef BU2))
    )
   )
   (net (rename N82 "rd_data_count<5>")
    (joined
      (portRef (member rd_data_count 2))
      (portRef (member rd_data_count 2) (instanceRef BU2))
    )
   )
   (net (rename N83 "rd_data_count<4>")
    (joined
      (portRef (member rd_data_count 3))
      (portRef (member rd_data_count 3) (instanceRef BU2))
    )
   )
   (net (rename N84 "rd_data_count<3>")
    (joined
      (portRef (member rd_data_count 4))
      (portRef (member rd_data_count 4) (instanceRef BU2))
    )
   )
   (net (rename N85 "rd_data_count<2>")
    (joined
      (portRef (member rd_data_count 5))
      (portRef (member rd_data_count 5) (instanceRef BU2))
    )
   )
   (net (rename N86 "rd_data_count<1>")
    (joined
      (portRef (member rd_data_count 6))
      (portRef (member rd_data_count 6) (instanceRef BU2))
    )
   )
   (net (rename N87 "rd_data_count<0>")
    (joined
      (portRef (member rd_data_count 7))
      (portRef (member rd_data_count 7) (instanceRef BU2))
    )
   )
   (net (rename N90 "wr_data_count<7>")
    (joined
      (portRef (member wr_data_count 0))
      (portRef (member wr_data_count 0) (instanceRef BU2))
    )
   )
   (net (rename N91 "wr_data_count<6>")
    (joined
      (portRef (member wr_data_count 1))
      (portRef (member wr_data_count 1) (instanceRef BU2))
    )
   )
   (net (rename N92 "wr_data_count<5>")
    (joined
      (portRef (member wr_data_count 2))
      (portRef (member wr_data_count 2) (instanceRef BU2))
    )
   )
   (net (rename N93 "wr_data_count<4>")
    (joined
      (portRef (member wr_data_count 3))
      (portRef (member wr_data_count 3) (instanceRef BU2))
    )
   )
   (net (rename N94 "wr_data_count<3>")
    (joined
      (portRef (member wr_data_count 4))
      (portRef (member wr_data_count 4) (instanceRef BU2))
    )
   )
   (net (rename N95 "wr_data_count<2>")
    (joined
      (portRef (member wr_data_count 5))
      (portRef (member wr_data_count 5) (instanceRef BU2))
    )
   )
   (net (rename N96 "wr_data_count<1>")
    (joined
      (portRef (member wr_data_count 6))
      (portRef (member wr_data_count 6) (instanceRef BU2))
    )
   )
   (net (rename N97 "wr_data_count<0>")
    (joined
      (portRef (member wr_data_count 7))
      (portRef (member wr_data_count 7) (instanceRef BU2))
    )
   )
))))
(design async_fifo_8_8_128 (cellRef async_fifo_8_8_128 (libraryRef test_lib))
  (property X_CORE_INFO (string "fifo_generator_v2_2, Coregen 7.1.04i_ip3"))
  (property PART (string "xc2vp70-ff1704-7") (owner "Xilinx")))
)