src/edu/berkeley/fleet/fpga/bee2/async_fifo_8_8_128.v

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  29 // The synopsys directives "translate_off/translate_on" specified below are
  30 // supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
  31 // tools. Ensure they are correct for your synthesis tool(s).
  32
  33 // You must compile the wrapper file async_fifo_8_8_128.v when simulating
  34 // the core, async_fifo_8_8_128. When compiling the wrapper file, be sure to
  35 // reference the XilinxCoreLib Verilog simulation library. For detailed
  36 // instructions, please refer to the "CORE Generator Help".
  37
  38 `timescale 1ns/1ps
  39
  40 module async_fifo_8_8_128(
  41         din,
  42         rd_clk,
  43         rd_en,
  44         rst,
  45         wr_clk,
  46         wr_en,
  47         dout,
  48         empty,
  49         full,
  50         rd_data_count,
  51         wr_data_count);
  52
  53
  54 input [7 : 0] din;
  55 input rd_clk;
  56 input rd_en;
  57 input rst;
  58 input wr_clk;
  59 input wr_en;
  60 output [7 : 0] dout;
  61 output empty;
  62 output full;
  63 output [7 : 0] rd_data_count;
  64 output [7 : 0] wr_data_count;
  65
  66 // synopsys translate_off
  67
  68       FIFO_GENERATOR_V2_2 #(
  69                 0,      // c_common_clock
  70                 0,      // c_count_type
  71                 2,      // c_data_count_width
  72                 "BlankString",  // c_default_value
  73                 8,      // c_din_width
  74                 "0",    // c_dout_rst_val
  75                 8,      // c_dout_width
  76                 0,      // c_enable_rlocs
  77                 "virtex2p",     // c_family
  78                 0,      // c_has_almost_empty
  79                 0,      // c_has_almost_full
  80                 0,      // c_has_backup
  81                 0,      // c_has_data_count
  82                 0,      // c_has_meminit_file
  83                 0,      // c_has_overflow
  84                 1,      // c_has_rd_data_count
  85                 0,      // c_has_rd_rst
  86                 1,      // c_has_rst
  87                 0,      // c_has_underflow
  88                 0,      // c_has_valid
  89                 0,      // c_has_wr_ack
  90                 1,      // c_has_wr_data_count
  91                 0,      // c_has_wr_rst
  92                 2,      // c_implementation_type
  93                 0,      // c_init_wr_pntr_val
  94                 1,      // c_memory_type
  95                 "BlankString",  // c_mif_file_name
  96                 0,      // c_optimization_mode
  97                 0,      // c_overflow_low
  98                 0,      // c_preload_latency
  99                 1,      // c_preload_regs
 100                 512,    // c_prim_fifo_type
 101                 32,     // c_prog_empty_thresh_assert_val
 102                 32,     // c_prog_empty_thresh_negate_val
 103                 0,      // c_prog_empty_type
 104                 96,     // c_prog_full_thresh_assert_val
 105                 96,     // c_prog_full_thresh_negate_val
 106                 0,      // c_prog_full_type
 107                 8,      // c_rd_data_count_width
 108                 128,    // c_rd_depth
 109                 7,      // c_rd_pntr_width
 110                 0,      // c_underflow_low
 111                 0,      // c_use_fifo16_flags
 112                 0,      // c_valid_low
 113                 0,      // c_wr_ack_low
 114                 8,      // c_wr_data_count_width
 115                 128,    // c_wr_depth
 116                 7,      // c_wr_pntr_width
 117                 1)      // c_wr_response_latency
 118         inst (
 119                 .DIN(din),
 120                 .RD_CLK(rd_clk),
 121                 .RD_EN(rd_en),
 122                 .RST(rst),
 123                 .WR_CLK(wr_clk),
 124                 .WR_EN(wr_en),
 125                 .DOUT(dout),
 126                 .EMPTY(empty),
 127                 .FULL(full),
 128                 .RD_DATA_COUNT(rd_data_count),
 129                 .WR_DATA_COUNT(wr_data_count),
 130                 .CLK(),
 131                 .BACKUP(),
 132                 .BACKUP_MARKER(),
 133                 .PROG_EMPTY_THRESH(),
 134                 .PROG_EMPTY_THRESH_ASSERT(),
 135                 .PROG_EMPTY_THRESH_NEGATE(),
 136                 .PROG_FULL_THRESH(),
 137                 .PROG_FULL_THRESH_ASSERT(),
 138                 .PROG_FULL_THRESH_NEGATE(),
 139                 .RD_RST(),
 140                 .WR_RST(),
 141                 .ALMOST_EMPTY(),
 142                 .ALMOST_FULL(),
 143                 .DATA_COUNT(),
 144                 .OVERFLOW(),
 145                 .PROG_EMPTY(),
 146                 .PROG_FULL(),
 147                 .VALID(),
 148                 .UNDERFLOW(),
 149                 .WR_ACK());
 150
 151
 152 // synopsys translate_on
 153
 154 endmodule
 155