40nm omega counter: switch design to use a timing constraint.

[fleet.git] / chips / omegaCounter / 40nm / electric / purpleFive.jelib

diff --git a/chips/omegaCounter/40nm/electric/purpleFive.jelib b/chips/omegaCounter/40nm/electric/purpleFive.jelib
index 960e101..6911755 100644 (file)
--- a/chips/omegaCounter/40nm/electric/purpleFive.jelib
+++ b/chips/omegaCounter/40nm/electric/purpleFive.jelib
@@ -1,5 +1,5 @@
 # header information:
-HpurpleFive|8.10g|USER_electrical_units()I70464
+HpurpleFive|8.10h|USER_electrical_units()I70464
 
 # Views:
 Vdocumentation|doc
@@ -15,21 +15,22 @@ LredFive|redFive
 # Tools:
 Ouser|DefaultTechnology()Scmos90|SchematicTechnology()Scmos90
 Oio|GDSOutputConvertsBracketsInExports()BF|GDSWritesExportPins()BT
+OSTA|GlobalSDCCommands()S"\n### 4 GHz clock setup\ncreate_clock -period 0.250 -name clk -waveform \"0 0.125\" clk\nset_clock_uncertainty -setup 0.010 clk\nset_clock_uncertainty -hold 0.010 clk\nset_propagated_clock clk\nset_clock_transition -rise 0.030 clk\nset_clock_transition -fall 0.030 clk\n#set_driving_cell -lib_cell inv_X008_0 clk\n\n### remove scan path from timing\nset_false_path -through */so\nset_false_path -from {sin}\nset_false_path -from {scanEn}\nset_false_path -to {sout}\n"
 
 # Technologies:
 Tcmos90|"GDS(ST)LayerForPad-FrameINcmos90"()S43|"GDS(TSMC)LayerForPad-FrameINcmos90"()S43
 Tmocmos|SelectedFoundryFormocmos()STSMC
 
 # Cell LEsettings;1{ic}
-CLEsettings;1{ic}||artwork|1023920563000|1252708283504|E|ATTR_LESETTINGS(D5G1;HNPX1.5;Y-4;)I1|ATTR_alpha(D5G1;HNPX1.5;Y-2;)D0.7|ATTR_epsilon(D5G1;HNPX1.5;Y1;)S0.01|ATTR_gate_cap(D5G1;HNPX1.5;Y-1;)F0.4|ATTR_keeper_ratio(D5G1;HNPX1.5;Y-3;)F0.1|ATTR_max_iter(D5G1;HNPX1.5;)I40|ATTR_su(D5G1;HNPX1.5;Y3;)S4.5|ATTR_wire_ratio(D5G1;HNPX1.5;Y2;)S0.22|prototype_center()I[0,0]
+CLEsettings;1{ic}||artwork|1023920563000|1253203134284|E|ATTR_LESETTINGS(D5G1;HNPX1.5;Y-4;)I1|ATTR_alpha(D5G1;HNPX1.5;Y-2;)S0.7|ATTR_epsilon(D5G1;HNPX1.5;Y1;)S0.01|ATTR_gate_cap(D5G1;HNPX1.5;Y-1;)S0.4|ATTR_keeper_ratio(D5G1;HNPX1.5;Y-3;)F0.1|ATTR_max_iter(D5G1;HNPX1.5;)I40|ATTR_su(D5G1;HNPX1.5;Y3;)S4.5|ATTR_wire_ratio(D5G1;HNPX1.5;Y2;)S0.22|ATTR_x1inverter_length(D5G1;HNPX1.5;Y-6;)I4|ATTR_x1inverter_nwidth(D5G1;HNPX1.5;Y-7;)I12|ATTR_x1inverter_pwidth(D5G1;HNPX1.5;Y-8;)S24|prototype_center()I[0,0]
 Ngeneric:Facet-Center|art@0||0|0||||AV
-NBox|art@2||1.5|-0.5|9|9|||ART_color()I-1728014079
+NBox|art@2||1.5|-2.75|11|13.5|||ART_color()I-1174339839
 Ngeneric:Invisible-Pin|pin@0||1.5|4.5|||||ART_message(D5G1;)S[LEsettings]
 X
 
-# Cell LEsettings;1{sch}
-CLEsettings;1{sch}||schematic|1023920036000|1213471981644||ATTR_LESETTINGS(D6G1;HNPX-21;Y23;)I1|ATTR_alpha(D5G1;HNPX-18.5;Y25;)D0.7|ATTR_epsilon(D6G1;HNPX-21;Y28;)S0.01|ATTR_gate_cap(D6G1;HNPX-21;Y26;)F0.4|ATTR_keeper_ratio(D5G1;HNPX-17;Y24;)F0.1|ATTR_max_iter(D6G1;HNPX-21;Y27;)I40|ATTR_su(D6G1;HNPX-21;Y30;)S4.5|ATTR_wire_ratio(D6G1;HNPX-21;Y29;)S0.22|ATTR_SPICE_template(D5G1;NTX-7;Y9;)S**LEsettings: None needed for LEsettings|prototype_center()I[12000,48000]
-ILEsettings;1{ic}|LEsettin@2||-4|2|||D5G4;|ATTR_LESETTINGS(D6G1;NPX-4;Y-3.5;)I1|ATTR_alpha(D5G1;NPX-1.5;Y-1.5;)F0.7|ATTR_epsilon(D6G1;NPX-4;Y1.5;)F0.0010|ATTR_gate_cap(D6G1;NPX-4;Y-0.5;)F0.19|ATTR_keeper_ratio(D5G1;NPY-2.5;)F0.1|ATTR_max_iter(D6G1;NPX-4;Y0.5;)I30|ATTR_su(D6G1;NPX-4;Y3.5;)S3.7|ATTR_wire_ratio(D6G1;NPX-4;Y2.5;)F0.16
+# Cell LEsettings;2{sch}
+CLEsettings;2{sch}||schematic|1023920036000|1253147132016||ATTR_LESETTINGS(D6G1;HNPX-21;Y23;)I1|ATTR_alpha(D5G1;HNPX-18.5;Y25;)S0.7|ATTR_epsilon(D6G1;HNPX-21;Y28;)S0.01|ATTR_gate_cap(D6G1;HNPX-21;Y26;)S0.4|ATTR_keeper_ratio(D5G1;HNPX-17;Y24;)F0.1|ATTR_max_iter(D6G1;HNPX-21;Y27;)I40|ATTR_su(D6G1;HNPX-21;Y30;)S4.5|ATTR_wire_ratio(D6G1;HNPX-21;Y29;)S0.22|ATTR_x1inverter_length(D5G1;HNPX-18.75;Y17;)I4|ATTR_x1inverter_nwidth(D5G1;HNPX-18.75;Y18;)I12|ATTR_x1inverter_pwidth(D5G1;HNPX-18.75;Y19;)S24|ATTR_SPICE_template(D5G1;NTX-25;Y2;)S**LEsettings: None needed for LEsettings|prototype_center()I[12000,48000]
+ILEsettings;1{ic}|LEsettin@5||-1|0|||D5G4;|ATTR_LESETTINGS(D5G1;NPY-1.5;)I1|ATTR_alpha(D5G1;NPY0.5;)S0.7|ATTR_epsilon(D5G1;NPY3.5;)S0.01|ATTR_gate_cap(D5G1;NPY1.5;)S0.4|ATTR_keeper_ratio(D5G1;NPY-0.5;)F0.1|ATTR_max_iter(D5G1;NPY2.5;)I40|ATTR_su(D5G1;NPY5.5;)S4.5|ATTR_wire_ratio(D5G1;NPY4.5;)S0.22|ATTR_x1inverter_length(D5G1;NPY-3.5;)I4|ATTR_x1inverter_nwidth(D5G1;NPY-4.5;)I12|ATTR_x1inverter_pwidth(D5G1;NPY-5.5;)S24
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Ngeneric:Invisible-Pin|pin@0||-9.5|12|||||ART_message(D6G1;)S[this is the diffusion effort of PMOS gates (Cdiffp/Cgate)]
 Ngeneric:Invisible-Pin|pin@1||-9.5|13|||||ART_message(D6G1;)S[this is the diffusion effort of NMOS gates (Cdiffn/Cgate)]
@@ -39,6 +40,9 @@ Ngeneric:Invisible-Pin|pin@4||-9.5|16|||||ART_message(D6G1;)S[epsilon is the con
 Ngeneric:Invisible-Pin|pin@5||-9.5|17|||||ART_message(D6G1;)S[wire ratio is the default wire ratio: Cwire/Cgate]
 Ngeneric:Invisible-Pin|pin@6||-9.5|18|||||ART_message(D6G1;)S[su is the global step-up (fan-out)]
 Ngeneric:Invisible-Pin|pin@7||-24|21|||||ART_message(D6G2;)S[This Facet is used to set Logical Effort Settings]
+Ngeneric:Invisible-Pin|pin@8||-9.5|11|||||ART_message(D6G1;)Sx1inverter_nwidth is the width of the nmos in an X=1 inverter
+Ngeneric:Invisible-Pin|pin@9||-9.5|10|||||ART_message(D6G1;)Sx1inverter_pwidth is the width of the pmos in an X=1 inverter
+Ngeneric:Invisible-Pin|pin@10||-9.5|9|||||ART_message(D6G1;)Sx1inverter_length is the length of the pmos and nmos in an X=1 inverter
 X
 
 # Cell aChangeRecord;1{doc}