40nm omega counter: switch design to use a timing constraint.

[fleet.git] / chips / omegaCounter / 40nm / header.hsp

diff --git a/chips/omegaCounter/40nm/header.hsp b/chips/omegaCounter/40nm/header.hsp
index 15d02b0..c445ef8 100644 (file)
--- a/chips/omegaCounter/40nm/header.hsp
+++ b/chips/omegaCounter/40nm/header.hsp
@@ -58,13 +58,13 @@ vvdd vdd gnd 'sup'
 * .param HSIMPRINTSIMSTATUS=1
 * .param HSIMOUTPUTFLUSH=1n
 
-* .param HSIMSPEED=8
+.param HSIMSPEED=8
 
 * for extracted-layout simulation
-.param HSIMPOSTL=3
+* .param HSIMPOSTL=3
 
 * I used to use HSIMSPEED=5, but the omega counter has simulation artifacts at that level
-.param HSIMSPEED=4
+* .param HSIMSPEED=4
 
 * defaults -- play with these?
 * .param HSIMSPEED=3