improve master-clear logic
[fleet.git] / src / com / sun / vlsi / chips / marina / test / MarinaTest.java
index 4d6f5e2..91a3944 100644 (file)
@@ -14,6 +14,7 @@ import com.sun.async.test.JtagSubchainTesterModel;
 import com.sun.async.test.JtagTester;
 import com.sun.async.test.ManualPowerChannel;
 import com.sun.async.test.NanosimModel;
+import com.sun.async.test.NanosimLogicSettable;
 import com.sun.async.test.HsimModel;
 import com.sun.async.test.VerilogModel;
 import com.sun.async.test.Netscan4;
@@ -262,20 +263,30 @@ public class MarinaTest {
 
         marina = new Marina(ccs, model, !cmdArgs.jtagShift, indenter);
 
+        if (model instanceof NanosimModel) {
+            NanosimLogicSettable mc = (NanosimLogicSettable)
+                ((SimulationModel)model).createLogicSettable(Marina.MASTER_CLEAR);
+            mc.setInitState(true);
+        }
+
+        prln("starting model");
         if (model instanceof VerilogModel)
             ((SimulationModel)model).start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift);
         else if (model instanceof HsimModel)
             ((SimulationModel)model).start("hsim64", netListName, 0, !cmdArgs.jtagShift);
         else
             ((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift);
+        prln("model started");
 
-        /*
-        ccC.resetInBits();
-        ccC.shift(Marina.CONTROL_CHAIN, false, true);
-        */
+        model.waitNS(1000);
+        prln("deasserting master clear");
+        ((SimulationModel)model).setNodeState(Marina.MASTER_CLEAR, 0);
+        model.waitNS(1000);
 
-        cc.resetInBits();
-        cc.shift(Marina.CONTROL_CHAIN, false, true);
+        if (cmdArgs.testNum!=0 && cmdArgs.testNum!=1) {
+            cc.resetInBits();
+            cc.shift(Marina.CONTROL_CHAIN, false, true);
+        }
         
         doOneTest(cmdArgs.testNum);