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+++ /dev/null
-
-projectname = bee2-control-user-fifo
-
-build_machine = sting.eecs.berkeley.edu
-build_machine_xilinx_path = /opt/xilinx/ISE9.2i_lin/
-build_machine_work_dir = ~/$(projectname)
-bee2_machine = bee441.megacz.com
-
-## you probably want to customize the stuff above this line
-
-## you probably don't want to change anything below this line
-
-xilinx = cd $(build_machine_work_dir);
-xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
-xilinx += XILINX=$(XILINX)
-xilinx += PATH=$$PATH:$(XILINX)/bin/lin
-xilinx += $(XILINX)/bin/lin/
-
-bitfile = bee2-control-user-fifo.bit
-
-remote_run = user_unprogram 1;
-remote_run += user_program 1 $(bitfile);
-remote_run += echo "Gdkkn+vnqkc " > /dev/selectmap1;
-remote_run += head -c12 /dev/selectmap1; echo
-
-verilog_files = $(find . -name \*.v)
-
-run: upload build/fpga/$(bitfile)
- ssh root@$(bee2_machine) '$(remote_run)'
-
-upload: build/fpga/$(bitfile)
- rsync -zare ssh --progress --verbose build/fpga/$(bitfile) root@$(bee2_machine):
-
-build/fpga/$(bitfile): $(verilog_files)
- mkdir -p build/fpga/
- rsync -zare ssh --progress --delete --verbose ./ ${build_machine}:${build_machine_work_dir}
- time ssh ${build_machine} 'make -C ${build_machine_work_dir} synth XILINX=${build_machine_xilinx_path}'
- scp ${build_machine}:${build_machine_work_dir}/main.bit build/fpga/$(bitfile)
-
-synth:
- mkdir -p build/fpga/
- echo work > main.lso
- for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
- mkdir -p tmp
- mkdir -p xst
- rm -rf build/fpga/_ngo
- $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
- $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
- $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
- $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
- $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
-# $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
+++ /dev/null
-
-projectname = working-bee2
-
-build_machine = sting.eecs.berkeley.edu
-build_machine_xilinx_path = /opt/xilinx/ISE9.2i_lin/
-build_machine_work_dir = ~/$(projectname)
-bee2_machine = board4
-
-## you probably want to customize the stuff above this line
-
-## you probably don't want to change anything below this line
-
-xilinx = cd $(build_machine_work_dir);
-xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
-xilinx += XILINX=$(XILINX)
-xilinx += PATH=$$PATH:$(XILINX)/bin/lin
-xilinx += $(XILINX)/bin/lin/
-
-bitfile = map0.bit
-
-remote_run = user_unprogram 1;
-remote_run += user_program 1 $(bitfile);
-
-verilog_files = $(find . -name \*.v)
-
-run: upload build/fpga/$(bitfile)
- ssh root@$(bee2_machine) '$(remote_run)'
-
-upload: build/fpga/$(bitfile)
- scp build/fpga/$(bitfile) root@$(bee2_machine):
-
-build/fpga/$(bitfile): $(verilog_files)
- mkdir -p build/fpga/
- rsync -zare --progress --delete --verbose ./ ${build_machine_work_dir}
- time ssh ${build_machine} 'make -C ${build_machine_work_dir} -f Makefile0 synth XILINX=${build_machine_xilinx_path}'
- cp main.bit build/fpga/$(bitfile)
-
-synth:
- mkdir -p build/fpga/
- echo work > main.lso
- for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
- mkdir -p tmp
- mkdir -p xst
- rm -rf build/fpga/_ngo
- $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
- $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
- $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
- $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
- $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
-# $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
+++ /dev/null
-
-projectname = working-bee2
-
-build_machine = sting.eecs.berkeley.edu
-build_machine_xilinx_path = /opt/xilinx/ISE9.2i_lin/
-build_machine_work_dir = ~/$(projectname)
-bee2_machine = board4
-
-## you probably want to customize the stuff above this line
-
-## you probably don't want to change anything below this line
-
-xilinx = cd $(build_machine_work_dir);
-xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
-xilinx += XILINX=$(XILINX)
-xilinx += PATH=$$PATH:$(XILINX)/bin/lin
-xilinx += $(XILINX)/bin/lin/
-
-bitfile = map1.bit
-
-remote_run = user_unprogram 2;
-remote_run += user_program 2 $(bitfile);
-remote_run += ./remote_run.pl;
-remote_run += cat transcript;
-
-verilog_files = $(find . -name \*.v)
-
-run: upload build/fpga/$(bitfile)
- ssh root@$(bee2_machine) '$(remote_run)'
-
-upload: build/fpga/$(bitfile)
- scp build/fpga/$(bitfile) root@$(bee2_machine):
-
-build/fpga/$(bitfile): $(verilog_files)
- mkdir -p build/fpga/
- rsync -zare --progress --delete --verbose ./ ${build_machine_work_dir}
- time ssh ${build_machine} 'make -C ${build_machine_work_dir} -f Makefile1 synth XILINX=${build_machine_xilinx_path}'
- cp main.bit build/fpga/$(bitfile)
- scp remote_run.pl root@$(bee2_machine):
-
-synth:
- mkdir -p build/fpga/
- echo work > main.lso
- for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
- mkdir -p tmp
- mkdir -p xst
- rm -rf build/fpga/_ngo
- $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
- $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
- $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
- $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
- $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
-# $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
+++ /dev/null
-
-projectname = bee2-control-user-fifo
-
-build_machine = sting.eecs.berkeley.edu
-build_machine_xilinx_path = /opt/xilinx/ISE9.2i_lin/
-build_machine_work_dir = ~/$(projectname)
-bee2_machine = board4
-
-## you probably want to customize the stuff above this line
-
-## you probably don't want to change anything below this line
-
-xilinx = cd $(build_machine_work_dir);
-xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
-xilinx += XILINX=$(XILINX)
-xilinx += PATH=$$PATH:$(XILINX)/bin/lin
-xilinx += $(XILINX)/bin/lin/
-
-bitfile = bee2-control-user-fifo.bit
-
-remote_run = user_unprogram 1;
-remote_run += user_program 1 $(bitfile);
-remote_run += ./remote_run.pl;
-remote_run += cat transcript;
-
-verilog_files = $(find . -name \*.v)
-
-run: upload build/fpga/$(bitfile)
- ssh root@$(bee2_machine) '$(remote_run)'
-
-upload: build/fpga/$(bitfile)
- scp build/fpga/$(bitfile) root@$(bee2_machine):
-
-build/fpga/$(bitfile): $(verilog_files)
- mkdir -p build/fpga/
- rsync -zare --progress --delete --verbose ./ ${build_machine_work_dir}
- time ssh ${build_machine} 'make -C ${build_machine_work_dir} synth XILINX=${build_machine_xilinx_path}'
- cp main.bit build/fpga/$(bitfile)
- scp remote_run.pl root@$(bee2_machine):
-
-synth:
- mkdir -p build/fpga/
- echo work > main.lso
- for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
- mkdir -p tmp
- mkdir -p xst
- rm -rf build/fpga/_ngo
- $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
- $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
- $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
- $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
- $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
-# $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf
+++ /dev/null
-Author: Tracy Wang
-
-Everything in this folder is the framework that I used to test the interchip on the Bee2.
-
-Here's a short list of important files and their description.
-
-============
-main.v
-
-This is the *generic* top level verilog file which hooks up the selectmap FIFOs (async_fifo_* files). Then it hooks the FIFOs to the testing file, in this case in root.v. Actual test resides in root.v.
-
-============
-main_counterexample_map0
-
-This is the main file which hooks up the counterexample Map0. So it hooks up the selectmap to BTN and SW. It also connects the interchip terminal to the right pins on Bee2.
-
-============
-main_counterexample_map1
-
-This is the main file which hooks up the counterexample Map1. It connects the counter outputs to the selectmap FIFO.
-
-============
-
-Makefile_userfpga
-
-This is the *generic* makefile which can be invoked from the control fpga to program the testing harness automatically onto one of the user fpgas. However, it will prompt for password in several locations, which I wasn't able to bypass.
-
-===========
-
-makemaps.pl
-
-This is the perl file which I used to invoke Makefile_interchip0 and Makefile interchip1 to build the two interchip maps. This file requires customization of the Makefile file names.
-Both Makefile_interchip0 and Makefile_interchip1 will program the bit files onto the boards. Makefile_interchip1 will actually run a remote_run.pl file after everything is programmed to automatically test the unit and retrieve the results.
-
-===========
-
-How to use selectmap
-
-To input characters into selectmap:
-
-echo "<characters here>" > /dev/selectmap[1-4];
-
-To read from selectmap
-
-head -c<number of characters> /dev/selectmap[1-4];
-
-i.e. if I'm on board 2, and I program a single unit which counts every time I receive a character from the selectmap, I would do the following
-
-echo "12345" > /dev/selectmap2;
-head -c5 /dev/selectmap2;
-
-i.e. if I'm on board1, and the interchip connects to board2, I would do something like
-
-echo "12345" > /dev/selectmap1;
-head -c5 /dev/selectmap2;
-
-===========
-
-Finally, step by step instructions on how to go from a verilog project to programming it and running it on the Bee2.
-
-1. Use RDLC to generate files from the RDL
-2. Copy all verilog files into a single flat directory on a server connected to a bee2 board (like sting)
-3. Make sure the selectmap FIFO, main*.v and Makefile* are also in that same directory.
-4. Customize the main*.v files to connect the right ports to selectmap FIFOs, and your Maps. If you have multiple Maps, make two separate main files
-5. Customize the Makefile to point to the right chip. If you are making two maps, make two Makefiles.
-6. Run Makefile. The original Makefiles will program the chips automatically.
-7. Use the above instructions to start running the tests by echoing characters into the selectmap.
+++ /dev/null
-(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
-(status (written (timeStamp 2006 2 18 19 6 14)
- (author "Xilinx, Inc.")
- (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 7.1.04i; Cores Update # 3"))))
- (comment "
- This file is owned and controlled by Xilinx and must be used
- solely for design, simulation, implementation and creation of
- design files limited to Xilinx devices or technologies. Use
- with non-Xilinx devices or technologies is expressly prohibited
- and immediately terminates your license.
-
- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- FOR A PARTICULAR PURPOSE.
-
- Xilinx products are not intended for use in life support
- appliances, devices, or systems. Use in such applications are
- expressly prohibited.
-
- (c) Copyright 1995-2005 Xilinx, Inc.
- All rights reserved.
-
- ")
- (comment "Core parameters: ")
- (comment "c_wr_response_latency = 1 ")
- (comment "c_has_rd_data_count = 1 ")
- (comment "c_din_width = 8 ")
- (comment "c_has_wr_data_count = 1 ")
- (comment "InstanceName = async_fifo_8_8_128 ")
- (comment "c_implementation_type = 2 ")
- (comment "c_family = virtex2p ")
- (comment "c_has_wr_rst = 0 ")
- (comment "c_underflow_low = 0 ")
- (comment "c_has_meminit_file = 0 ")
- (comment "c_has_overflow = 0 ")
- (comment "c_preload_latency = 0 ")
- (comment "c_dout_width = 8 ")
- (comment "c_rd_depth = 128 ")
- (comment "c_default_value = BlankString ")
- (comment "c_mif_file_name = BlankString ")
- (comment "c_has_underflow = 0 ")
- (comment "c_has_rd_rst = 0 ")
- (comment "c_has_almost_full = 0 ")
- (comment "c_has_rst = 1 ")
- (comment "c_data_count_width = 2 ")
- (comment "c_has_wr_ack = 0 ")
- (comment "c_wr_ack_low = 0 ")
- (comment "c_common_clock = 0 ")
- (comment "c_rd_pntr_width = 7 ")
- (comment "c_has_almost_empty = 0 ")
- (comment "c_rd_data_count_width = 8 ")
- (comment "c_enable_rlocs = 0 ")
- (comment "c_wr_pntr_width = 7 ")
- (comment "c_overflow_low = 0 ")
- (comment "c_prog_empty_type = 0 ")
- (comment "c_optimization_mode = 0 ")
- (comment "c_wr_data_count_width = 8 ")
- (comment "c_preload_regs = 1 ")
- (comment "c_dout_rst_val = 0 ")
- (comment "c_has_data_count = 0 ")
- (comment "c_prog_full_thresh_negate_val = 96 ")
- (comment "c_wr_depth = 128 ")
- (comment "c_prog_empty_thresh_negate_val = 32 ")
- (comment "c_prog_empty_thresh_assert_val = 32 ")
- (comment "c_has_valid = 0 ")
- (comment "c_init_wr_pntr_val = 0 ")
- (comment "c_prog_full_thresh_assert_val = 96 ")
- (comment "c_use_fifo16_flags = 0 ")
- (comment "c_has_backup = 0 ")
- (comment "c_valid_low = 0 ")
- (comment "c_prim_fifo_type = 512 ")
- (comment "c_count_type = 0 ")
- (comment "c_prog_full_type = 0 ")
- (comment "c_memory_type = 1 ")
- (external xilinxun (edifLevel 0)
- (technology (numberDefinition))
- (cell VCC (cellType GENERIC)
- (view view_1 (viewType NETLIST)
- (interface
- (port P (direction OUTPUT))
- )
- )
- )
- (cell GND (cellType GENERIC)
- (view view_1 (viewType NETLIST)
- (interface
- (port G (direction OUTPUT))
- )
- )
- )
- )
- (external async_fifo_8_8_128_fifo_generator_v2_2_xst_1_lib (edifLevel 0)
- (technology (numberDefinition))
- (cell async_fifo_8_8_128_fifo_generator_v2_2_xst_1 (cellType GENERIC)
- (view view_1 (viewType NETLIST)
- (interface
- (port clk (direction INPUT))
- (port backup (direction INPUT))
- (port backup_marker (direction INPUT))
- (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT))
- (port ( array ( rename prog_empty_thresh "prog_empty_thresh<6:0>") 7 ) (direction INPUT))
- (port ( array ( rename prog_empty_thresh_assert "prog_empty_thresh_assert<6:0>") 7 ) (direction INPUT))
- (port ( array ( rename prog_empty_thresh_negate "prog_empty_thresh_negate<6:0>") 7 ) (direction INPUT))
- (port ( array ( rename prog_full_thresh "prog_full_thresh<6:0>") 7 ) (direction INPUT))
- (port ( array ( rename prog_full_thresh_assert "prog_full_thresh_assert<6:0>") 7 ) (direction INPUT))
- (port ( array ( rename prog_full_thresh_negate "prog_full_thresh_negate<6:0>") 7 ) (direction INPUT))
- (port rd_clk (direction INPUT))
- (port rd_en (direction INPUT))
- (port rd_rst (direction INPUT))
- (port rst (direction INPUT))
- (port wr_clk (direction INPUT))
- (port wr_en (direction INPUT))
- (port wr_rst (direction INPUT))
- (port almost_empty (direction OUTPUT))
- (port almost_full (direction OUTPUT))
- (port ( array ( rename data_count "data_count<1:0>") 2 ) (direction OUTPUT))
- (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT))
- (port empty (direction OUTPUT))
- (port full (direction OUTPUT))
- (port overflow (direction OUTPUT))
- (port prog_empty (direction OUTPUT))
- (port prog_full (direction OUTPUT))
- (port valid (direction OUTPUT))
- (port ( array ( rename rd_data_count "rd_data_count<7:0>") 8 ) (direction OUTPUT))
- (port underflow (direction OUTPUT))
- (port wr_ack (direction OUTPUT))
- (port ( array ( rename wr_data_count "wr_data_count<7:0>") 8 ) (direction OUTPUT))
- )
- )
- )
- )
-(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
-(cell async_fifo_8_8_128
- (cellType GENERIC) (view view_1 (viewType NETLIST)
- (interface
- (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT))
- (port ( rename rd_clk "rd_clk") (direction INPUT))
- (port ( rename rd_en "rd_en") (direction INPUT))
- (port ( rename rst "rst") (direction INPUT))
- (port ( rename wr_clk "wr_clk") (direction INPUT))
- (port ( rename wr_en "wr_en") (direction INPUT))
- (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT))
- (port ( rename empty "empty") (direction OUTPUT))
- (port ( rename full "full") (direction OUTPUT))
- (port ( array ( rename rd_data_count "rd_data_count<7:0>") 8 ) (direction OUTPUT))
- (port ( array ( rename wr_data_count "wr_data_count<7:0>") 8 ) (direction OUTPUT))
- )
- (contents
- (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun))))
- (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun))))
- (instance BU2
- (viewRef view_1 (cellRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1 (libraryRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_lib)))
- )
- (net (rename N5 "din<7>")
- (joined
- (portRef (member din 0))
- (portRef (member din 0) (instanceRef BU2))
- )
- )
- (net (rename N6 "din<6>")
- (joined
- (portRef (member din 1))
- (portRef (member din 1) (instanceRef BU2))
- )
- )
- (net (rename N7 "din<5>")
- (joined
- (portRef (member din 2))
- (portRef (member din 2) (instanceRef BU2))
- )
- )
- (net (rename N8 "din<4>")
- (joined
- (portRef (member din 3))
- (portRef (member din 3) (instanceRef BU2))
- )
- )
- (net (rename N9 "din<3>")
- (joined
- (portRef (member din 4))
- (portRef (member din 4) (instanceRef BU2))
- )
- )
- (net (rename N10 "din<2>")
- (joined
- (portRef (member din 5))
- (portRef (member din 5) (instanceRef BU2))
- )
- )
- (net (rename N11 "din<1>")
- (joined
- (portRef (member din 6))
- (portRef (member din 6) (instanceRef BU2))
- )
- )
- (net (rename N12 "din<0>")
- (joined
- (portRef (member din 7))
- (portRef (member din 7) (instanceRef BU2))
- )
- )
- (net (rename N55 "rd_clk")
- (joined
- (portRef rd_clk)
- (portRef rd_clk (instanceRef BU2))
- )
- )
- (net (rename N56 "rd_en")
- (joined
- (portRef rd_en)
- (portRef rd_en (instanceRef BU2))
- )
- )
- (net (rename N58 "rst")
- (joined
- (portRef rst)
- (portRef rst (instanceRef BU2))
- )
- )
- (net (rename N59 "wr_clk")
- (joined
- (portRef wr_clk)
- (portRef wr_clk (instanceRef BU2))
- )
- )
- (net (rename N60 "wr_en")
- (joined
- (portRef wr_en)
- (portRef wr_en (instanceRef BU2))
- )
- )
- (net (rename N66 "dout<7>")
- (joined
- (portRef (member dout 0))
- (portRef (member dout 0) (instanceRef BU2))
- )
- )
- (net (rename N67 "dout<6>")
- (joined
- (portRef (member dout 1))
- (portRef (member dout 1) (instanceRef BU2))
- )
- )
- (net (rename N68 "dout<5>")
- (joined
- (portRef (member dout 2))
- (portRef (member dout 2) (instanceRef BU2))
- )
- )
- (net (rename N69 "dout<4>")
- (joined
- (portRef (member dout 3))
- (portRef (member dout 3) (instanceRef BU2))
- )
- )
- (net (rename N70 "dout<3>")
- (joined
- (portRef (member dout 4))
- (portRef (member dout 4) (instanceRef BU2))
- )
- )
- (net (rename N71 "dout<2>")
- (joined
- (portRef (member dout 5))
- (portRef (member dout 5) (instanceRef BU2))
- )
- )
- (net (rename N72 "dout<1>")
- (joined
- (portRef (member dout 6))
- (portRef (member dout 6) (instanceRef BU2))
- )
- )
- (net (rename N73 "dout<0>")
- (joined
- (portRef (member dout 7))
- (portRef (member dout 7) (instanceRef BU2))
- )
- )
- (net (rename N74 "empty")
- (joined
- (portRef empty)
- (portRef empty (instanceRef BU2))
- )
- )
- (net (rename N75 "full")
- (joined
- (portRef full)
- (portRef full (instanceRef BU2))
- )
- )
- (net (rename N80 "rd_data_count<7>")
- (joined
- (portRef (member rd_data_count 0))
- (portRef (member rd_data_count 0) (instanceRef BU2))
- )
- )
- (net (rename N81 "rd_data_count<6>")
- (joined
- (portRef (member rd_data_count 1))
- (portRef (member rd_data_count 1) (instanceRef BU2))
- )
- )
- (net (rename N82 "rd_data_count<5>")
- (joined
- (portRef (member rd_data_count 2))
- (portRef (member rd_data_count 2) (instanceRef BU2))
- )
- )
- (net (rename N83 "rd_data_count<4>")
- (joined
- (portRef (member rd_data_count 3))
- (portRef (member rd_data_count 3) (instanceRef BU2))
- )
- )
- (net (rename N84 "rd_data_count<3>")
- (joined
- (portRef (member rd_data_count 4))
- (portRef (member rd_data_count 4) (instanceRef BU2))
- )
- )
- (net (rename N85 "rd_data_count<2>")
- (joined
- (portRef (member rd_data_count 5))
- (portRef (member rd_data_count 5) (instanceRef BU2))
- )
- )
- (net (rename N86 "rd_data_count<1>")
- (joined
- (portRef (member rd_data_count 6))
- (portRef (member rd_data_count 6) (instanceRef BU2))
- )
- )
- (net (rename N87 "rd_data_count<0>")
- (joined
- (portRef (member rd_data_count 7))
- (portRef (member rd_data_count 7) (instanceRef BU2))
- )
- )
- (net (rename N90 "wr_data_count<7>")
- (joined
- (portRef (member wr_data_count 0))
- (portRef (member wr_data_count 0) (instanceRef BU2))
- )
- )
- (net (rename N91 "wr_data_count<6>")
- (joined
- (portRef (member wr_data_count 1))
- (portRef (member wr_data_count 1) (instanceRef BU2))
- )
- )
- (net (rename N92 "wr_data_count<5>")
- (joined
- (portRef (member wr_data_count 2))
- (portRef (member wr_data_count 2) (instanceRef BU2))
- )
- )
- (net (rename N93 "wr_data_count<4>")
- (joined
- (portRef (member wr_data_count 3))
- (portRef (member wr_data_count 3) (instanceRef BU2))
- )
- )
- (net (rename N94 "wr_data_count<3>")
- (joined
- (portRef (member wr_data_count 4))
- (portRef (member wr_data_count 4) (instanceRef BU2))
- )
- )
- (net (rename N95 "wr_data_count<2>")
- (joined
- (portRef (member wr_data_count 5))
- (portRef (member wr_data_count 5) (instanceRef BU2))
- )
- )
- (net (rename N96 "wr_data_count<1>")
- (joined
- (portRef (member wr_data_count 6))
- (portRef (member wr_data_count 6) (instanceRef BU2))
- )
- )
- (net (rename N97 "wr_data_count<0>")
- (joined
- (portRef (member wr_data_count 7))
- (portRef (member wr_data_count 7) (instanceRef BU2))
- )
- )
-))))
-(design async_fifo_8_8_128 (cellRef async_fifo_8_8_128 (libraryRef test_lib))
- (property X_CORE_INFO (string "fifo_generator_v2_2, Coregen 7.1.04i_ip3"))
- (property PART (string "xc2vp70-ff1704-7") (owner "Xilinx")))
-)
+++ /dev/null
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2005 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The synopsys directives "translate_off/translate_on" specified below are
-// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
-// tools. Ensure they are correct for your synthesis tool(s).
-
-// You must compile the wrapper file async_fifo_8_8_128.v when simulating
-// the core, async_fifo_8_8_128. When compiling the wrapper file, be sure to
-// reference the XilinxCoreLib Verilog simulation library. For detailed
-// instructions, please refer to the "CORE Generator Help".
-
-`timescale 1ns/1ps
-
-module async_fifo_8_8_128(
- din,
- rd_clk,
- rd_en,
- rst,
- wr_clk,
- wr_en,
- dout,
- empty,
- full,
- rd_data_count,
- wr_data_count);
-
-
-input [7 : 0] din;
-input rd_clk;
-input rd_en;
-input rst;
-input wr_clk;
-input wr_en;
-output [7 : 0] dout;
-output empty;
-output full;
-output [7 : 0] rd_data_count;
-output [7 : 0] wr_data_count;
-
-// synopsys translate_off
-
- FIFO_GENERATOR_V2_2 #(
- 0, // c_common_clock
- 0, // c_count_type
- 2, // c_data_count_width
- "BlankString", // c_default_value
- 8, // c_din_width
- "0", // c_dout_rst_val
- 8, // c_dout_width
- 0, // c_enable_rlocs
- "virtex2p", // c_family
- 0, // c_has_almost_empty
- 0, // c_has_almost_full
- 0, // c_has_backup
- 0, // c_has_data_count
- 0, // c_has_meminit_file
- 0, // c_has_overflow
- 1, // c_has_rd_data_count
- 0, // c_has_rd_rst
- 1, // c_has_rst
- 0, // c_has_underflow
- 0, // c_has_valid
- 0, // c_has_wr_ack
- 1, // c_has_wr_data_count
- 0, // c_has_wr_rst
- 2, // c_implementation_type
- 0, // c_init_wr_pntr_val
- 1, // c_memory_type
- "BlankString", // c_mif_file_name
- 0, // c_optimization_mode
- 0, // c_overflow_low
- 0, // c_preload_latency
- 1, // c_preload_regs
- 512, // c_prim_fifo_type
- 32, // c_prog_empty_thresh_assert_val
- 32, // c_prog_empty_thresh_negate_val
- 0, // c_prog_empty_type
- 96, // c_prog_full_thresh_assert_val
- 96, // c_prog_full_thresh_negate_val
- 0, // c_prog_full_type
- 8, // c_rd_data_count_width
- 128, // c_rd_depth
- 7, // c_rd_pntr_width
- 0, // c_underflow_low
- 0, // c_use_fifo16_flags
- 0, // c_valid_low
- 0, // c_wr_ack_low
- 8, // c_wr_data_count_width
- 128, // c_wr_depth
- 7, // c_wr_pntr_width
- 1) // c_wr_response_latency
- inst (
- .DIN(din),
- .RD_CLK(rd_clk),
- .RD_EN(rd_en),
- .RST(rst),
- .WR_CLK(wr_clk),
- .WR_EN(wr_en),
- .DOUT(dout),
- .EMPTY(empty),
- .FULL(full),
- .RD_DATA_COUNT(rd_data_count),
- .WR_DATA_COUNT(wr_data_count),
- .CLK(),
- .BACKUP(),
- .BACKUP_MARKER(),
- .PROG_EMPTY_THRESH(),
- .PROG_EMPTY_THRESH_ASSERT(),
- .PROG_EMPTY_THRESH_NEGATE(),
- .PROG_FULL_THRESH(),
- .PROG_FULL_THRESH_ASSERT(),
- .PROG_FULL_THRESH_NEGATE(),
- .RD_RST(),
- .WR_RST(),
- .ALMOST_EMPTY(),
- .ALMOST_FULL(),
- .DATA_COUNT(),
- .OVERFLOW(),
- .PROG_EMPTY(),
- .PROG_FULL(),
- .VALID(),
- .UNDERFLOW(),
- .WR_ACK());
-
-
-// synopsys translate_on
-
-endmodule
-
+++ /dev/null
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
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\7fa533=8381<7>t$03e>f5<@8897)li:29K560<akh1<75`d083>>{e9>81<7:50;2x 47a2jk0D<<=;I302>o2j3:17d99:188m47e2900ci?50;9~f41629086=4?{%32b?74=2B:>?5G1248m0d=831bo=4?::mg5?6=3th:;84?:583>5}#98l1ol5G1308L4513`?i6=44i6494?=n98h1<75`d083>>{e9>>1<7=50;2x 47a289>7E?=2:J273=n=k0;66gl0;29?jb62900qo?88;290?6=8r.:=k4la:J267=O9:<0e8l50;9j33<722c:=o4?::mg5?6=3th:;:4?:283>5}#98l1=>;4H001?M74>2c>n7>5;ha3>5<<gm;1<75rb05a>5<3290;w)?>f;ab?M75:2B:?;5f5c83>>o0>3:17d?>b;29?jb62900qo?ia;291?6=8r.:=k4m4:J267=O9:<0(oh50:k55?6=3`>j6=44i4g94?=n<10;66a>0`83>>{e9oi1<7;50;2x 47a2k>0D<<=;I302>"en3:0e;?50;9j0d<722c>i7>5;h6;>5<<g8:j6=44}c3e0?6=;3:1<v*>1g8270=O9;80D<=9;h7a>5<<aj:1<75`d083>>{e:9:1<7;50;2x 47a2k>0D<<=;I302>"en3:0e;?50;9j0d<722c>i7>5;h6;>5<<g8:j6=44}c3ea?6==3:1<v*>1g8a0>N6:;1C=>84$cd94>o193:17d:n:188m0c=831b854?::m24d<722wi=k;50;794?6|,8;m6o:4H001?M74>2.ij7>4i7394?=n<h0;66g:e;29?l2?2900c<>n:188yg7a>3:197>50z&25c<e>2B:>?5G1248 g`=:2c==7>5;h6b>5<<am=1<75f4983>>i68h0;66sm1g:94?3=83:p(<?i:c68L4453A;8:6*mf;28m37=831b8l4?::k6a?6=3`>36=44o02b>5<<uk;m>7>53;294~"69o0:?85G1308L4513`?i6=44ib294?=hl80;66sm1g194?2=83:p(<?i:bc8L4453A;8:6g:b;29?l112900e<?m:188ka7=831vn<k;:181>5<7s-;:j7m<;I316>"en380D<=9;h`a>5<<gm;1<75rb0g0>5<3290;w)?>f;ab?M75:2B:?;5f5c83>>o0>3:17d?>b;29?jb62900qo?m3;296?6=8r.:=k4l3:J267=#jo087E?<6:kaf?6=3fn:6=44}c3f3?6=<3:1<v*>1g8`e>N6:;1C=>84i4`94?=n??0;66g>1c83>>ic93:17pl>e783>6<729q/=<h51278L4453A;8:6g:b;29?le72900ci?50;9~f4cf290?6=4?{%32b?ef3A;9>6F>379j1g<722c<:7>5;h32f?6=3fn:6=44}c3f=?6=;3:1<v*>1g8270=O9;80D<=9;h7a>5<<aj:1<75`d083>>{e9ln1<7:50;2x 47a2jk0D<<=;I302>o2j3:17d99:188m47e2900ci?50;9~f4cd29086=4?{%32b?74=2B:>?5G1248m0d=831bo=4?::mg5?6=3th:j=4?:583>5}#98l1ol5G1308L4513`?i6=44i6494?=n98h1<75`d083>>{e:1>1<7:50;2x 47a2j20D<<=;%`e>77<@89=7dlm:188mge=831bni4?::m`5?6=3th8>44?:283>5}#98l1=>;4H001?M74>2c>n7>5;ha3>5<<gm;1<75rb234>5<4290;w)?>f;301>N6:;1C=>84i4`94?=nk90;66ak1;29?xd4<=0;6>4?:1y'54`=9:?0D<<=;I302>o2j3:17dm?:188ka7=831vn>;j:180>5<7s-;:j7?<5:J267=O9:<0e8l50;9jg5<722eo=7>5;|`20`<72=0;6=u+10d9gd=O9;80D<=9;h7a>5<<a><1<75f10`94?=hl80;66sm15c94?5=83:p(<?i:016?M75:2B:?;5f5c83>>od83:17bj>:188yg41>3:187>50z&25c<e;2B:>?5G1248m37=831b9h4?::k7<?6=3f;;m7>5;|`11c<72=0;6=u+10d9f6=O9;80D<=9;h42>5<<a<o1<75f4983>>i68h0;66sm15`94?2=83:p(<?i:bc8L4453A;8:6g:b;29?l112900e<?m:188ka7=831vn>o?:180>5<7s-;:j7m:;I316>"en3?0D<=9;h`a>5<<aki1<75`d083>>{e;1>1<7;50;2x 47a2j30D<<=;%`e>66<@89=7dlm:188mge=831bni4?::kaa?6=3fn:6=44}c157?6=<3:1<v*>1g8`3>N6:;1/nk48;I302>oej3:17dll:188mgb=831dh<4?::
\7fa6g?=83>1<7>t$03e>g5<@8897E?<6:J71>"en3:0e;?50;9j1`<722c?47>5;n33e?6=3th94;4?:583>5}#98l1o55G1308 g`=:81C=>84ic`94?=njj0;66gmd;29?je62900qo=9f;291?6=8r.:=k4l9:J267=#jo09>6F>379jfg<722cio7>5;h`g>5<<ako1<75`d083>>{e9==1<7:50;2x 47a2jk0D<<=;I302>o2j3:17d99:188m47e2900ci?50;9~f42?29096=4?{%32b?e43A;9>6*mf;08L4513`hi6=44oe394?=zj8?<6=4;:183
\7f!76n3ij7E?=2:J273=n=k0;66g86;29?l76j3:17bj>:188yg72<3:187>50z&25c<di2B:>?5G1248m0d=831b;;4?::k25g<722eo=7>5;|`225<72<0;6=u+10d9f1=O9;80D<=9;%`e>5=n>80;66g;a;29?l3b2900e9650;9l55g=831vn<;j:186>5<7s-;:j7l;;I316>N6;?1/nk4?;h42>5<<a=k1<75f5d83>>o303:17b??a;29?xd6=j0;684?:1y'54`=j=1C=?<4H015?!da291b:<4?::k7e?6=3`?n6=44i5:94?=h99k1<75rb355>5<3290;w)?>f;`0?M75:2B:?;5f6083>>o2m3:17d:7:188k46f2900qo?:a;291?6=8r.:=k4m4:J267=O9:<0(oh50:k55?6=3`>j6=44i4g94?=n<10;66a>0`83>>{e9<31<7;50;2x 47a2k>0D<<=;I302>"en3:0e;?50;9j0d<722c>i7>5;h6;>5<<g8:j6=44}c36<?6=;3:1<v*>1g8270=O9;80D<=9;h7a>5<<aj:1<75`d083>>{e9?>1<7;50;2x 47a2k>0D<<=;I302>"en3:0e;?50;9j0d<722c>i7>5;h6;>5<<g8:j6=44}c356?6==3:1<v*>1g8a0>N6:;1C=>84$cd94>o193:17d:n:188m0c=831b854?::m24d<722wi>:m50;694?6|,8;m6n64H001?!da2;;0D<=9;h`a>5<<aki1<75fbe83>>id93:17pl=6183>1<729q/=<h5b29K574<@89=7d8>:188m0c=831b854?::m24d<722wi>;?50;694?6|,8;m6o=4H001?M74>2c==7>5;h7f>5<<a=21<75`11c94?=zj;<96=4;:183
\7f!76n3h87E?=2:J273=n>80;66g:e;29?l2?2900c<>n:188yg41;3:187>50z&25c<e;2B:>?5G1248m37=831b9h4?::k7<?6=3f;;m7>5;|`121<72=0;6=u+10d9f6=O9;80D<=9;h42>5<<a<o1<75f4983>>i68h0;66sm27794?2=83:p(<?i:c18L4453A;8:6g91;29?l3b2900e9650;9l55g=831vn?;7:187>5<7s-;:j7l<;I316>N6;?1b:<4?::k6a?6=3`>36=44o02b>5<<uk8>57>54;294~"69o0i?6F>239K560<a?;1<75f5d83>>o303:17b??a;29?xd5=h0;694?:1y'54`=j:1C=?<4H015?l062900e8k50;9j0=<722e:<l4?::
\7fa60d=83>1<7>t$03e>g5<@8897E?<6:k55?6=3`?n6=44i5:94?=h99k1<75rb37`>5<3290;w)?>f;`0?M75:2B:?;5f6083>>o2m3:17d:7:188k46f2900qo<:d;290?6=8r.:=k4m3:J267=O9:<0e;?50;9j1`<722c?47>5;n33e?6=3th99h4?:583>5}#98l1n>5G1308L4513`<:6=44i4g94?=n<10;66a>0`83>>{e;;o1<7=50;2x 47a2j<0D<<=;%`e>7`<@89=7dlm:188mge=831do<4?::
\7fa77b=83>1<7>t$03e>fg<@8897E?<6:k6f?6=3`==6=44i03a>5<<gm;1<75rb20`>5<4290;w)?>f;301>N6:;1C=>84i4`94?=nk90;66ak1;29?xd4;;0;6>4?:1y'54`=k?1C=?<4$cd96c=O9:<0eol50;9jff<722eh=7>5;|`074<72=0;6=u+10d9gd=O9;80D<=9;h7a>5<<a><1<75f10`94?=hl80;66sm32294?5=83:p(<?i:016?M75:2B:?;5f5c83>>od83:17bj>:188yg54>3:1?7>50z&25c<d>2B:>?5+bg81b>N6;?1bno4?::kag?6=3fi:6=44}c101?6=<3:1<v*>1g8`e>N6:;1C=>84i4`94?=n??0;66g>1c83>>ic93:17pl<3583>6<729q/=<h51278L4453A;8:6g:b;29?le72900ci?50;9~f65f29086=4?{%32b?e23A;9>6*mf;0e?M74>2cin7>5;h``>5<<gm;1<75rb21:>5<3290;w)?>f;ab?M75:2B:?;5f5c83>>o0>3:17d?>b;29?jb62900qo=<8;297?6=8r.:=k4>349K574<@89=7d;m:188mf6=831dh<4?::
\7fa76`=8391<7>t$03e>f0<@8897)li:3d8L4513`hi6=44ica94?=hk80;66sm32g94?2=83:p(<?i:bc8L4453A;8:6g:b;29?l112900e<?m:188ka7=831vn>=k:180>5<7s-;:j7?<5:J267=O9:<0e8l50;9jg5<722eo=7>5;|`006<72:0;6=u+10d9g3=O9;80(oh52g9K560<akh1<75fbb83>>id93:17pl<4383>1<729q/=<h5c`9K574<@89=7d;m:188m20=831b=<l50;9l`4<722wi?9?50;194?6|,8;m6<=:;I316>N6;?1b9o4?::k`4?6=3fn:6=44}c171?6=;3:1<v*>1g8`2>N6:;1/nk4=f:J273=njk0;66gmc;29?je62900qo<88;290?6=8r.:=k4l7:J267=#jo0?56F>379jfg<722cio7>5;h`g>5<<gm;1<75rb26:>5<4290;w)?>f;a5?M75:2.ij7<i;I302>oej3:17dll:188kf7=831vn>:7:187>5<7s-;:j7mn;I316>N6;?1b9o4?::k42?6=3`;:n7>5;nf2>5<<uk9?;7>53;294~"69o0:?85G1308L4513`?i6=44ib294?=hl80;66sm35f94?5=83:p(<?i:b48L4453-hm6?h4H015?lde2900eom50;9lg4<722wi?9m50;694?6|,8;m6no4H001?M74>2c>n7>5;h55>5<<a8;i6=44oe394?=zj:>i6=4<:183
\7f!76n3;896F>239K560<a<h1<75fc183>>ic93:17pl<5083>6<729q/=<h5c79K574<,kl1>k5G1248mgd=831bnn4?::m`5?6=3th89=4?:583>5}#98l1ol5G1308L4513`?i6=44i6494?=n98h1<75`d083>>{e;=l1<7=50;2x 47a289>7E?=2:J273=n=k0;66gl0;29?jb62900qo=:5;297?6=8r.:=k4l6:J267=#jo09j6F>379jfg<722cio7>5;na2>5<<uk9>87>54;294~"69o0hm6F>239K560<a<h1<75f7783>>o69k0;66ak1;29?xd4=:0;6>4?:1y'54`=9:?0D<<=;I302>o2j3:17dm?:188ka7=831vn>;6:180>5<7s-;:j7m9;I316>"en38m7E?<6:kaf?6=3`hh6=44ob394?=zj:?36=4;:183
\7f!76n3ij7E?=2:J273=n=k0;66g86;29?l76j3:17bj>:188yg52?3:1?7>50z&25c<6;<1C=?<4H015?l3e2900en>50;9l`4<722wi?8j50;194?6|,8;m6n84H001?!da2;l0D<=9;h`a>5<<aki1<75`c083>>{e;<i1<7:50;2x 47a2jk0D<<=;I302>o2j3:17d99:188m47e2900ci?50;9~f63e29086=4?{%32b?74=2B:>?5G1248m0d=831bo=4?::mg5?6=3th89k4?:283>5}#98l1o;5G1308 g`=:o1C=>84ic`94?=njj0;66al1;29?xd5?l0;694?:1y'54`=k11C=?<4$cd964=O9:<0eol50;9jff<722cih7>5;na2>5<<uk9;57>52;294~"69o0h86F>239'fc<53A;8:6gmb;29?je62900qo=?8;290?6=8r.:=k4la:J267=O9:<0e8l50;9j33<722c:=o4?::mg5?6=3th9<<4?:383>5}#98l1o>5G1308 g`=;2B:?;5fbc83>>ic93:17pl<0b83>1<729q/=<h5c`9K574<@89=7d;m:188m20=831b=<l50;9l`4<722wi?=l50;194?6|,8;m6<=:;I316>N6;?1b9o4?::k`4?6=3fn:6=44}c13b?6=<3:1<v*>1g8`e>N6:;1C=>84i4`94?=n??0;66g>1c83>>ic93:17pl<0d83>6<729q/=<h51278L4453A;8:6g:b;29?le72900ci?50;9~f675290?6=4?{%32b?ef3A;9>6F>379j1g<722c<:7>5;h32f?6=3fn:6=44}c125?6=;3:1<v*>1g8270=O9;80D<=9;h7a>5<<aj:1<75`d083>>{e;8?1<7:50;2x 47a2jk0D<<=;I302>o2j3:17d99:188m47e2900ci?50;9~f67329086=4?{%32b?74=2B:>?5G1248m0d=831bo=4?::mg5?6=3th8=54?:583>5}#98l1ol5G1308L4513`?i6=44i6494?=n98h1<75`d083>>{e;8h1<7<50;2x 47a2j>0D<<=;%`e>7=O9:<0eol50;9lg4<722wi?<o50;694?6|,8;m6no4H001?M74>2c>n7>5;h55>5<<a8;i6=44oe394?=zj:286=4::183
\7f!76n3i27E?=2:&ab?573A;8:6gmb;29?ldd2900eoj50;9jf`<722eo=7>5;|`05`<72=0;6=u+10d9gd=O9;80D<=9;h7a>5<<a><1<75f10`94?=hl80;66sm30f94?5=83:p(<?i:016?M75:2B:?;5f5c83>>od83:17bj>:188yg5593:187>50z&25c<di2B:>?5G1248m0d=831b;;4?::k25g<722eo=7>5;|`065<72:0;6=u+10d9563<@8897E?<6:k6f?6=3`i;6=44oe394?=zj:8?6=4;:183
\7f!76n3ij7E?=2:J273=n=k0;66g86;29?l76j3:17bj>:188yg55;3:1?7>50z&25c<6;<1C=?<4H015?l3e2900en>50;9l`4<722wi??950;694?6|,8;m6no4H001?M74>2c>n7>5;h55>5<<a8;i6=44oe394?=zj:8=6=4<:183
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\7f!76n3h87E?=2:J273=n>80;66g:e;29?l2?2900c<>n:188yg72;3:1?7>50z&25c<6;<1C=?<4H015?l3e2900en>50;9l`4<722wi?;;50;794?6|,8;m6n74H001?!da2=80D<=9;h`a>5<<aki1<75fbe83>>oem3:17bj>:188yg5193:187>50z&25c<d?2B:>?5+bg8a5>N6;?1bno4?::kag?6=3`ho6=44oe394?=zj:<=6=4;:183
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\7fxFG
\ No newline at end of file
+++ /dev/null
-(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
-(status (written (timeStamp 2006 2 18 19 6 6)
- (author "Xilinx, Inc.")
- (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 7.1.04i; Cores Update # 3"))))
- (comment "
- This file is owned and controlled by Xilinx and must be used
- solely for design, simulation, implementation and creation of
- design files limited to Xilinx devices or technologies. Use
- with non-Xilinx devices or technologies is expressly prohibited
- and immediately terminates your license.
-
- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'
- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- FOR A PARTICULAR PURPOSE.
-
- Xilinx products are not intended for use in life support
- appliances, devices, or systems. Use in such applications are
- expressly prohibited.
-
- (c) Copyright 1995-2005 Xilinx, Inc.
- All rights reserved.
-
- ")
- (comment "Core parameters: ")
- (comment "c_reg_inputsb = 0 ")
- (comment "c_reg_inputsa = 0 ")
- (comment "c_has_ndb = 0 ")
- (comment "c_has_nda = 0 ")
- (comment "c_ytop_addr = 1024 ")
- (comment "c_has_rfdb = 0 ")
- (comment "c_has_rfda = 0 ")
- (comment "c_ywea_is_high = 1 ")
- (comment "c_yena_is_high = 1 ")
- (comment "InstanceName = async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst ")
- (comment "c_yhierarchy = hierarchy1 ")
- (comment "c_yclka_is_rising = 1 ")
- (comment "c_family = virtex2p ")
- (comment "c_ysinita_is_high = 1 ")
- (comment "c_ybottom_addr = 0 ")
- (comment "c_width_b = 8 ")
- (comment "c_width_a = 8 ")
- (comment "c_sinita_value = 0000 ")
- (comment "c_sinitb_value = 00 ")
- (comment "c_limit_data_pitch = 18 ")
- (comment "c_write_modeb = 0 ")
- (comment "c_write_modea = 0 ")
- (comment "c_has_rdyb = 0 ")
- (comment "c_yuse_single_primitive = 0 ")
- (comment "c_has_rdya = 0 ")
- (comment "c_addra_width = 7 ")
- (comment "c_addrb_width = 7 ")
- (comment "c_has_limit_data_pitch = 0 ")
- (comment "c_default_data = 0000 ")
- (comment "c_pipe_stages_b = 0 ")
- (comment "c_yweb_is_high = 1 ")
- (comment "c_yenb_is_high = 1 ")
- (comment "c_pipe_stages_a = 0 ")
- (comment "c_yclkb_is_rising = 1 ")
- (comment "c_yydisable_warnings = 1 ")
- (comment "c_enable_rlocs = 0 ")
- (comment "c_ysinitb_is_high = 1 ")
- (comment "c_has_web = 0 ")
- (comment "c_has_default_data = 1 ")
- (comment "c_has_wea = 1 ")
- (comment "c_has_sinitb = 1 ")
- (comment "c_has_sinita = 1 ")
- (comment "c_has_dinb = 0 ")
- (comment "c_has_dina = 1 ")
- (comment "c_ymake_bmm = 0 ")
- (comment "c_has_enb = 1 ")
- (comment "c_has_ena = 0 ")
- (comment "c_mem_init_file = mif_file_16_1 ")
- (comment "c_depth_b = 128 ")
- (comment "c_depth_a = 128 ")
- (comment "c_has_doutb = 1 ")
- (comment "c_has_douta = 0 ")
- (comment "c_yprimitive_type = 4kx4 ")
- (external xilinxun (edifLevel 0)
- (technology (numberDefinition))
- (cell VCC (cellType GENERIC)
- (view view_1 (viewType NETLIST)
- (interface
- (port P (direction OUTPUT))
- )
- )
- )
- (cell GND (cellType GENERIC)
- (view view_1 (viewType NETLIST)
- (interface
- (port G (direction OUTPUT))
- )
- )
- )
- (cell RAMB16_S9_S9 (cellType GENERIC)
- (view view_1 (viewType NETLIST)
- (interface
- (port WEA (direction INPUT))
- (port ENA (direction INPUT))
- (port SSRA (direction INPUT))
- (port CLKA (direction INPUT))
- (port (rename DIA_0_ "DIA<0>") (direction INPUT))
- (port (rename DIA_1_ "DIA<1>") (direction INPUT))
- (port (rename DIA_2_ "DIA<2>") (direction INPUT))
- (port (rename DIA_3_ "DIA<3>") (direction INPUT))
- (port (rename DIA_4_ "DIA<4>") (direction INPUT))
- (port (rename DIA_5_ "DIA<5>") (direction INPUT))
- (port (rename DIA_6_ "DIA<6>") (direction INPUT))
- (port (rename DIA_7_ "DIA<7>") (direction INPUT))
- (port (rename DOA_0_ "DOA<0>") (direction OUTPUT))
- (port (rename DOA_1_ "DOA<1>") (direction OUTPUT))
- (port (rename DOA_2_ "DOA<2>") (direction OUTPUT))
- (port (rename DOA_3_ "DOA<3>") (direction OUTPUT))
- (port (rename DOA_4_ "DOA<4>") (direction OUTPUT))
- (port (rename DOA_5_ "DOA<5>") (direction OUTPUT))
- (port (rename DOA_6_ "DOA<6>") (direction OUTPUT))
- (port (rename DOA_7_ "DOA<7>") (direction OUTPUT))
- (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT))
- (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT))
- (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT))
- (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT))
- (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT))
- (port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT))
- (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT))
- (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
- (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
- (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
- (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
- (port (rename DIPA_0_ "DIPA<0>") (direction INPUT))
- (port (rename DOPA_0_ "DOPA<0>") (direction OUTPUT))
- (port WEB (direction INPUT))
- (port ENB (direction INPUT))
- (port SSRB (direction INPUT))
- (port CLKB (direction INPUT))
- (port (rename DIB_0_ "DIB<0>") (direction INPUT))
- (port (rename DIB_1_ "DIB<1>") (direction INPUT))
- (port (rename DIB_2_ "DIB<2>") (direction INPUT))
- (port (rename DIB_3_ "DIB<3>") (direction INPUT))
- (port (rename DIB_4_ "DIB<4>") (direction INPUT))
- (port (rename DIB_5_ "DIB<5>") (direction INPUT))
- (port (rename DIB_6_ "DIB<6>") (direction INPUT))
- (port (rename DIB_7_ "DIB<7>") (direction INPUT))
- (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
- (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
- (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
- (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
- (port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
- (port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
- (port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
- (port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
- (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
- (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
- (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
- (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
- (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
- (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
- (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
- (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
- (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
- (port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT))
- (port (rename ADDRB_10_ "ADDRB<10>") (direction INPUT))
- (port (rename DIPB_0_ "DIPB<0>") (direction INPUT))
- (port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT))
- )
- )
- )
- )
-(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
-(cell async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst
- (cellType GENERIC) (view view_1 (viewType NETLIST)
- (interface
- (port ( rename dina_7_ "dina<7>") (direction INPUT))
- (port ( rename dina_6_ "dina<6>") (direction INPUT))
- (port ( rename dina_5_ "dina<5>") (direction INPUT))
- (port ( rename dina_4_ "dina<4>") (direction INPUT))
- (port ( rename dina_3_ "dina<3>") (direction INPUT))
- (port ( rename dina_2_ "dina<2>") (direction INPUT))
- (port ( rename dina_1_ "dina<1>") (direction INPUT))
- (port ( rename dina_0_ "dina<0>") (direction INPUT))
- (port ( rename dinb_7_ "dinb<7>") (direction INPUT))
- (port ( rename dinb_6_ "dinb<6>") (direction INPUT))
- (port ( rename dinb_5_ "dinb<5>") (direction INPUT))
- (port ( rename dinb_4_ "dinb<4>") (direction INPUT))
- (port ( rename dinb_3_ "dinb<3>") (direction INPUT))
- (port ( rename dinb_2_ "dinb<2>") (direction INPUT))
- (port ( rename dinb_1_ "dinb<1>") (direction INPUT))
- (port ( rename dinb_0_ "dinb<0>") (direction INPUT))
- (port ( rename ena "ena") (direction INPUT))
- (port ( rename enb "enb") (direction INPUT))
- (port ( rename wea "wea") (direction INPUT))
- (port ( rename web "web") (direction INPUT))
- (port ( rename sinita "sinita") (direction INPUT))
- (port ( rename sinitb "sinitb") (direction INPUT))
- (port ( rename nda "nda") (direction INPUT))
- (port ( rename ndb "ndb") (direction INPUT))
- (port ( rename clka "clka") (direction INPUT))
- (port ( rename clkb "clkb") (direction INPUT))
- (port ( rename addra_6_ "addra<6>") (direction INPUT))
- (port ( rename addra_5_ "addra<5>") (direction INPUT))
- (port ( rename addra_4_ "addra<4>") (direction INPUT))
- (port ( rename addra_3_ "addra<3>") (direction INPUT))
- (port ( rename addra_2_ "addra<2>") (direction INPUT))
- (port ( rename addra_1_ "addra<1>") (direction INPUT))
- (port ( rename addra_0_ "addra<0>") (direction INPUT))
- (port ( rename addrb_6_ "addrb<6>") (direction INPUT))
- (port ( rename addrb_5_ "addrb<5>") (direction INPUT))
- (port ( rename addrb_4_ "addrb<4>") (direction INPUT))
- (port ( rename addrb_3_ "addrb<3>") (direction INPUT))
- (port ( rename addrb_2_ "addrb<2>") (direction INPUT))
- (port ( rename addrb_1_ "addrb<1>") (direction INPUT))
- (port ( rename addrb_0_ "addrb<0>") (direction INPUT))
- (port ( rename rdya "rdya") (direction OUTPUT))
- (port ( rename rdyb "rdyb") (direction OUTPUT))
- (port ( rename rfda "rfda") (direction OUTPUT))
- (port ( rename rfdb "rfdb") (direction OUTPUT))
- (port ( rename douta_7_ "douta<7>") (direction OUTPUT))
- (port ( rename douta_6_ "douta<6>") (direction OUTPUT))
- (port ( rename douta_5_ "douta<5>") (direction OUTPUT))
- (port ( rename douta_4_ "douta<4>") (direction OUTPUT))
- (port ( rename douta_3_ "douta<3>") (direction OUTPUT))
- (port ( rename douta_2_ "douta<2>") (direction OUTPUT))
- (port ( rename douta_1_ "douta<1>") (direction OUTPUT))
- (port ( rename douta_0_ "douta<0>") (direction OUTPUT))
- (port ( rename doutb_7_ "doutb<7>") (direction OUTPUT))
- (port ( rename doutb_6_ "doutb<6>") (direction OUTPUT))
- (port ( rename doutb_5_ "doutb<5>") (direction OUTPUT))
- (port ( rename doutb_4_ "doutb<4>") (direction OUTPUT))
- (port ( rename doutb_3_ "doutb<3>") (direction OUTPUT))
- (port ( rename doutb_2_ "doutb<2>") (direction OUTPUT))
- (port ( rename doutb_1_ "doutb<1>") (direction OUTPUT))
- (port ( rename doutb_0_ "doutb<0>") (direction OUTPUT))
- )
- (contents
- (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun))))
- (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun))))
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- (joined
- (portRef doutb_6_)
- (portRef DOB_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
- )
- )
- (net (rename N56 "doutb<5>")
- (joined
- (portRef doutb_5_)
- (portRef DOB_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
- )
- )
- (net (rename N57 "doutb<4>")
- (joined
- (portRef doutb_4_)
- (portRef DOB_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
- )
- )
- (net (rename N58 "doutb<3>")
- (joined
- (portRef doutb_3_)
- (portRef DOB_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
- )
- )
- (net (rename N59 "doutb<2>")
- (joined
- (portRef doutb_2_)
- (portRef DOB_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
- )
- )
- (net (rename N60 "doutb<1>")
- (joined
- (portRef doutb_1_)
- (portRef DOB_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
- )
- )
- (net (rename N61 "doutb<0>")
- (joined
- (portRef doutb_0_)
- (portRef DOB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8))
- )
- )
-))))
-(design async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst (cellRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst (libraryRef test_lib))
- (property X_CORE_INFO (string "null"))
- (property PART (string "XC2VP20-6-ff896") (owner "Xilinx")))
-)
+++ /dev/null
-######################################
-## System clock pins
-######################################
-
-NET User_Clk PERIOD=100MHz;
-
-NET Clkin_p LOC = AP21 | IOSTANDARD = LVDS_25;
-NET Clkin_m LOC = AN21 | IOSTANDARD = LVDS_25;
-
-######################################
-## SelectMAP interface pins
-######################################
-
-NET D_I<0> LOC = AU9 | IOSTANDARD = LVCMOS25;
-NET D_I<1> LOC = AV9 | IOSTANDARD = LVCMOS25;
-NET D_I<2> LOC = AY9 | IOSTANDARD = LVCMOS25;
-NET D_I<3> LOC = AW9 | IOSTANDARD = LVCMOS25;
-NET D_I<4> LOC = AW34 | IOSTANDARD = LVCMOS25;
-NET D_I<5> LOC = AY34 | IOSTANDARD = LVCMOS25;
-NET D_I<6> LOC = AV34 | IOSTANDARD = LVCMOS25;
-NET D_I<7> LOC = AU34 | IOSTANDARD = LVCMOS25;
-
-NET RDWR_B LOC = AR34 | IOSTANDARD = LVCMOS25;
-NET CS_B LOC = AT34 | IOSTANDARD = LVCMOS25;
-NET INIT_B LOC = AR9 | IOSTANDARD = LVCMOS25;
-NET CCLK LOC = C14 | IOSTANDARD = LVCMOS25;
-
-NET gpleds<1> LOC = AB6 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<2> LOC = AB7 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<3> LOC = AB9 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<4> LOC = AB10 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<5> LOC = AD7 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<6> LOC = AF1 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
+++ /dev/null
--w
--g DebugBitstream:No
--g Binary:no
--g CRC:Enable
--g ConfigRate:4
--g CclkPin:PullUp
--g M0Pin:PullUp
--g M1Pin:PullUp
--g M2Pin:PullUp
--g ProgPin:PullUp
--g DonePin:PullUp
--g PowerdownPin:PullUp
--g TckPin:PullUp
--g TdiPin:PullUp
--g TdoPin:PullNone
--g TmsPin:PullUp
--g UnusedPin:PullDown
--g UserID:0xFFFFFFFF
--g DCMShutdown:Disable
--g DisableBandgap:No
--g DCIUpdateMode:AsRequired
--g StartUpClk:CClk
--g DONE_cycle:4
--g GTS_cycle:5
--g GWE_cycle:6
--g LCK_cycle:NoWait
--g Security:None
--g DonePipe:No
--g DriveDone:No
--g Encrypt:No
-
-
-
-
-
-
-
+++ /dev/null
-`timescale 1ps / 1ps
-
-// Copyright (c) 2005-2006, Regents of the University of California
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-// - Neither the name of the University of California, Berkeley nor the
-// names of its contributors may be used to endorse or promote
-// products derived from this software without specific prior
-// written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-//----------------------------------------------------------------------------
-// user_fifo.v
-//----------------------------------------------------------------------------
-
-`timescale 1ps / 1ps
-
-module user_fifo
- (
- // FIFO interface ports
- WrFifo_Din, // Write FIFO data-in
- WrFifo_WrEn, // Write FIFO write enable
- WrFifo_Full, // Write FIFO full
- WrFifo_WrCnt, // Write FIFO write count
- RdFifo_Dout, // Read FIFO data-out
- RdFifo_RdEn, // Read FIFO read enable
- RdFifo_Empty, // Read FIFO empty
- RdFifo_RdCnt, // Read FIFO read count
- User_Rst, // User reset
- User_Clk, // User clock
- Sys_Rst, // System clock reset
- Sys_Clk, // 100MHz system clock for CCLK generation
-
- // SelectMAP interface ports
- D_I, // Data bus input
- D_O, // Data bus output
- D_T, // Data bus tristate enable
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK // CCLK output
- );
-
- // FIFO interface ports
- input [0:7] WrFifo_Din;
- input WrFifo_WrEn;
- output WrFifo_Full;
- output [0:7] WrFifo_WrCnt;
- output [0:7] RdFifo_Dout;
- input RdFifo_RdEn;
- output RdFifo_Empty;
- output [0:7] RdFifo_RdCnt;
- input User_Rst;
- input User_Clk;
- input Sys_Rst;
- input Sys_Clk;
-
- // SelectMAP protocol ports
- input [0:7] D_I;
- output [0:7] D_O;
- output [0:7] D_T;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
-
- // ____ __ _ _ _ _ //
- // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ //
- // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| //
- // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ //
- // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ //
- // //
-
- //----------------------------------------------------------------------------
- // Signal definitions
- //----------------------------------------------------------------------------
- // Write FIFO signals
- wire [0:7] WrFifo_Dout;
- wire WrFifo_Empty;
- wire WrFifo_RdEn;
- wire [0:7] WrFifo_RdCnt;
- wire [0:7] WrFifo_RdCnt_int;
- wire [0:7] WrFifo_WrCnt_int;
-
- // Read FIFO signals
- wire [0:7] RdFifo_Din;
- wire RdFifo_Full;
- wire RdFifo_WrEn;
- wire [0:7] RdFifo_WrCnt;
- wire [0:7] RdFifo_WrCnt_int;
- wire [0:7] RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // IO Registers
- //----------------------------------------------------------------------------
- reg CCLK;
-
- reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true;
- reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true;
- reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true;
- reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true;
- reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true;
-
- // Outputs
- assign D_O = D_O_reg;
- assign INIT_B = INIT_B_reg;
-
- // Inputs
- always @( posedge Sys_Clk )
- begin
- D_I_reg <= D_I;
- RDWR_B_reg <= RDWR_B;
- CS_B_reg <= CS_B;
- end
-
- //----------------------------------------------------------------------------
- // Generate CCLK and associated reset
- //----------------------------------------------------------------------------
- reg SYNC_done;
- reg SYNC_done_dly;
- reg CS_B_reg_dly;
-
- always @( posedge Sys_Clk )
- begin
- CS_B_reg_dly <= CS_B_reg;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done <= 1'b0;
- else if (RDWR_B_reg && ~CS_B_reg)
- SYNC_done <= 1'b1;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done_dly <= 1'b0;
- else
- SYNC_done_dly <= SYNC_done;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- CCLK <= 1'b0;
- else if (~CS_B_reg && CS_B_reg_dly && CCLK)
- CCLK <= 1'b1;
- else
- CCLK <= ~CCLK;
- end
-
- // _____ ___ _____ ___ //
- // | ___|_ _| ___/ _ \ ___ //
- // | |_ | || |_ | | | / __| //
- // | _| | || _|| |_| \__ \ //
- // |_| |___|_| \___/|___/ //
- // //
- // Write FIFO: The write is with respect to the user. The user writes data to this
- // FIFO and the control side of SelectMAP reads the data.
- //
- // Read FIFO: The read is with respect to the user. The user reads data sent from the
- // control side of SelectMAP.
- //
-
- //----------------------------------------------------------------------------
- // Read FIFO
- //----------------------------------------------------------------------------
- assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK;
- assign RdFifo_Din = D_I_reg;
-
- async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ),
- .dout( RdFifo_Dout ),
- .rd_clk( User_Clk ),
- .rd_en( RdFifo_RdEn ),
- .wr_clk( Sys_Clk ),
- .wr_en( RdFifo_WrEn ),
- .rst( User_Rst ),
- .empty( RdFifo_Empty ),
- .full( RdFifo_Full ),
- .rd_data_count( RdFifo_RdCnt_int ),
- .wr_data_count( RdFifo_WrCnt_int ) );
-
- assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int;
- assign RdFifo_RdCnt = RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // Write FIFO
- //----------------------------------------------------------------------------
- assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK;
-
- async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ),
- .dout( WrFifo_Dout ),
- .rd_clk( Sys_Clk ),
- .rd_en( WrFifo_RdEn ),
- .wr_clk( User_Clk ),
- .wr_en( WrFifo_WrEn ),
- .rst( User_Rst ),
- .empty( WrFifo_Empty ),
- .full( WrFifo_Full ),
- .rd_data_count( WrFifo_RdCnt_int ),
- .wr_data_count( WrFifo_WrCnt_int ) );
-
- assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int;
- assign WrFifo_RdCnt = WrFifo_RdCnt_int;
-
- // ____ _ _ __ __ _ ____ //
- // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ //
- // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | //
- // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ //
- // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| //
- // //
-
- //----------------------------------------------------------------------------
- // SelectMAP control outputs
- //----------------------------------------------------------------------------
- wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt;
-
- assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending
-
- always @( posedge Sys_Clk )
- begin
- D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout;
- INIT_B_reg <= WrFifo_Empty;
- end
-
- //----------------------------------------------------------------------------
-
-endmodule
-
-
-module main
- (
- // User clock ports
- Clkin_p,
- Clkin_m,
-
- // SelectMAP interface ports
- D, // Data bus
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK, // Local CCLK output
- gpleds
- );
-
- // User clock/reset ports
- input Clkin_p;
- input Clkin_m;
-
- // SelectMAP protocol ports
- inout [0:7] D;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
- output [6:1] gpleds;
-
-
- // Wires
- wire CCLK_int;
-
- wire [0:31] LoopData;
- wire [0:31] LoopDataW;
- wire LoopEmpty;
- wire LoopFull;
-
- wire [0:7] D_I;
- wire [0:7] D_O;
- wire [0:7] D_T;
-
- wire User_Clk;
- wire User_Rst;
-
- reg [6:1] gpleds_reg;
-
- // synthesis attribute tig of activate_r is yes;
- wire activate_r;
- // synthesis attribute tig of activate_a is yes;
- wire activate_a;
-
- wire [7:0] write_data;
- wire write_enable;
- wire write_full;
-
- wire [7:0] read_data;
- wire read_empty;
- wire [7:0] read_wire;
-
- reg [7:0] write_reg;
- reg [7:0] read_reg;
- wire read_enable;
-
- root my_root(User_Clk,
- read_empty, read_enable, read_data,
- write_full, write_enable, write_data);
-
- // IO buffers
- OBUF obuf_cclk( .I( CCLK_int ),
- .O( CCLK )
- );
-
- IOBUF iobuf_d0( .I( D_O[0] ),
- .IO( D[0] ),
- .O( D_I[0] ),
- .T( D_T[0] )
- );
-
- IOBUF iobuf_d1( .I( D_O[1] ),
- .IO( D[1] ),
- .O( D_I[1] ),
- .T( D_T[1] )
- );
-
- IOBUF iobuf_d2( .I( D_O[2] ),
- .IO( D[2] ),
- .O( D_I[2] ),
- .T( D_T[2] )
- );
-
- IOBUF iobuf_d3( .I( D_O[3] ),
- .IO( D[3] ),
- .O( D_I[3] ),
- .T( D_T[3] )
- );
-
- IOBUF iobuf_d4( .I( D_O[4] ),
- .IO( D[4] ),
- .O( D_I[4] ),
- .T( D_T[4] )
- );
-
- IOBUF iobuf_d5( .I( D_O[5] ),
- .IO( D[5] ),
- .O( D_I[5] ),
- .T( D_T[5] )
- );
-
- IOBUF iobuf_d6( .I( D_O[6] ),
- .IO( D[6] ),
- .O( D_I[6] ),
- .T( D_T[6] )
- );
-
- IOBUF iobuf_d7( .I( D_O[7] ),
- .IO( D[7] ),
- .O( D_I[7] ),
- .T( D_T[7] )
- );
-
- // Clock buffer and reset
- IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
- .IB( Clkin_m ),
- .O( User_Clk )
- );
-
- wire [0:3] rst;
-
- FD rst0( .D( 1'b0 ),
- .Q( rst[0] ),
- .C( User_Clk )
- );
- defparam rst0.INIT = 1'b1;
-
- FD rst1( .D( rst[0] ),
- .Q( rst[1] ),
- .C( User_Clk )
- );
- defparam rst1.INIT = 1'b1;
-
- FD rst2( .D( rst[1] ),
- .Q( rst[2] ),
- .C( User_Clk )
- );
- defparam rst2.INIT = 1'b1;
-
- FD rst3( .D( rst[2] ),
- .Q( rst[3] ),
- .C( User_Clk )
- );
- defparam rst3.INIT = 1'b1;
-
- assign User_Rst = |rst;
-
-
- // FIFO module instantiation
- user_fifo test_fifo(
- .WrFifo_Din( write_data ),
- .WrFifo_WrEn( write_enable ),
- .WrFifo_Full( write_full ),
- .WrFifo_WrCnt( ),
- .RdFifo_Dout( read_data ),
- .RdFifo_RdEn( read_enable ),
- .RdFifo_Empty( read_empty ),
- .RdFifo_RdCnt( ),
- .User_Rst( User_Rst ),
- .User_Clk( User_Clk ),
- .Sys_Rst( User_Rst ),
- .Sys_Clk( User_Clk ),
- .D_I( D_I ),
- .D_O( D_O ),
- .D_T( D_T ),
- .RDWR_B( RDWR_B ),
- .CS_B( CS_B ),
- .INIT_B( INIT_B ),
- .CCLK( CCLK_int )
- );
-
-endmodule
+++ /dev/null
-set -tmpdir ./tmp
-set -xsthdpdir ./xst
-run
--ifn main.prj -ifmt mixed -ofn main -ofmt NGC -p xc2vp70-6-ff1704 -top main -opt_mode Speed -opt_level 1 -iuc NO -lso main.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract Yes -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract NO -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 1 -register_duplication YES -register_balancing No -slice_packing No -optimize_primitives NO -tristate2logic Yes -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5
+++ /dev/null
-`timescale 1ps / 1ps
-
-// Copyright (c) 2005-2006, Regents of the University of California
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-// - Neither the name of the University of California, Berkeley nor the
-// names of its contributors may be used to endorse or promote
-// products derived from this software without specific prior
-// written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-//----------------------------------------------------------------------------
-// user_fifo.v
-//----------------------------------------------------------------------------
-
-`timescale 1ps / 1ps
-
-module user_fifo
- (
- // FIFO interface ports
- WrFifo_Din, // Write FIFO data-in
- WrFifo_WrEn, // Write FIFO write enable
- WrFifo_Full, // Write FIFO full
- WrFifo_WrCnt, // Write FIFO write count
- RdFifo_Dout, // Read FIFO data-out
- RdFifo_RdEn, // Read FIFO read enable
- RdFifo_Empty, // Read FIFO empty
- RdFifo_RdCnt, // Read FIFO read count
- User_Rst, // User reset
- User_Clk, // User clock
- Sys_Rst, // System clock reset
- Sys_Clk, // 100MHz system clock for CCLK generation
-
- // SelectMAP interface ports
- D_I, // Data bus input
- D_O, // Data bus output
- D_T, // Data bus tristate enable
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK // CCLK output
- );
-
- // FIFO interface ports
- input [0:7] WrFifo_Din;
- input WrFifo_WrEn;
- output WrFifo_Full;
- output [0:7] WrFifo_WrCnt;
- output [0:7] RdFifo_Dout;
- input RdFifo_RdEn;
- output RdFifo_Empty;
- output [0:7] RdFifo_RdCnt;
- input User_Rst;
- input User_Clk;
- input Sys_Rst;
- input Sys_Clk;
-
- // SelectMAP protocol ports
- input [0:7] D_I;
- output [0:7] D_O;
- output [0:7] D_T;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
-
- // ____ __ _ _ _ _ //
- // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ //
- // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| //
- // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ //
- // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ //
- // //
-
- //----------------------------------------------------------------------------
- // Signal definitions
- //----------------------------------------------------------------------------
- // Write FIFO signals
- wire [0:7] WrFifo_Dout;
- wire WrFifo_Empty;
- wire WrFifo_RdEn;
- wire [0:7] WrFifo_RdCnt;
- wire [0:7] WrFifo_RdCnt_int;
- wire [0:7] WrFifo_WrCnt_int;
-
- // Read FIFO signals
- wire [0:7] RdFifo_Din;
- wire RdFifo_Full;
- wire RdFifo_WrEn;
- wire [0:7] RdFifo_WrCnt;
- wire [0:7] RdFifo_WrCnt_int;
- wire [0:7] RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // IO Registers
- //----------------------------------------------------------------------------
- reg CCLK;
-
- reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true;
- reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true;
- reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true;
- reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true;
- reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true;
-
- // Outputs
- assign D_O = D_O_reg;
- assign INIT_B = INIT_B_reg;
-
- // Inputs
- always @( posedge Sys_Clk )
- begin
- D_I_reg <= D_I;
- RDWR_B_reg <= RDWR_B;
- CS_B_reg <= CS_B;
- end
-
- //----------------------------------------------------------------------------
- // Generate CCLK and associated reset
- //----------------------------------------------------------------------------
- reg SYNC_done;
- reg SYNC_done_dly;
- reg CS_B_reg_dly;
-
- always @( posedge Sys_Clk )
- begin
- CS_B_reg_dly <= CS_B_reg;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done <= 1'b0;
- else if (RDWR_B_reg && ~CS_B_reg)
- SYNC_done <= 1'b1;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done_dly <= 1'b0;
- else
- SYNC_done_dly <= SYNC_done;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- CCLK <= 1'b0;
- else if (~CS_B_reg && CS_B_reg_dly && CCLK)
- CCLK <= 1'b1;
- else
- CCLK <= ~CCLK;
- end
-
- // _____ ___ _____ ___ //
- // | ___|_ _| ___/ _ \ ___ //
- // | |_ | || |_ | | | / __| //
- // | _| | || _|| |_| \__ \ //
- // |_| |___|_| \___/|___/ //
- // //
- // Write FIFO: The write is with respect to the user. The user writes data to this
- // FIFO and the control side of SelectMAP reads the data.
- //
- // Read FIFO: The read is with respect to the user. The user reads data sent from the
- // control side of SelectMAP.
- //
-
- //----------------------------------------------------------------------------
- // Read FIFO
- //----------------------------------------------------------------------------
- assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK;
- assign RdFifo_Din = D_I_reg;
-
- async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ),
- .dout( RdFifo_Dout ),
- .rd_clk( User_Clk ),
- .rd_en( RdFifo_RdEn ),
- .wr_clk( Sys_Clk ),
- .wr_en( RdFifo_WrEn ),
- .rst( User_Rst ),
- .empty( RdFifo_Empty ),
- .full( RdFifo_Full ),
- .rd_data_count( RdFifo_RdCnt_int ),
- .wr_data_count( RdFifo_WrCnt_int ) );
-
- assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int;
- assign RdFifo_RdCnt = RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // Write FIFO
- //----------------------------------------------------------------------------
- assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK;
-
- async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ),
- .dout( WrFifo_Dout ),
- .rd_clk( Sys_Clk ),
- .rd_en( WrFifo_RdEn ),
- .wr_clk( User_Clk ),
- .wr_en( WrFifo_WrEn ),
- .rst( User_Rst ),
- .empty( WrFifo_Empty ),
- .full( WrFifo_Full ),
- .rd_data_count( WrFifo_RdCnt_int ),
- .wr_data_count( WrFifo_WrCnt_int ) );
-
- assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int;
- assign WrFifo_RdCnt = WrFifo_RdCnt_int;
-
- // ____ _ _ __ __ _ ____ //
- // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ //
- // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | //
- // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ //
- // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| //
- // //
-
- //----------------------------------------------------------------------------
- // SelectMAP control outputs
- //----------------------------------------------------------------------------
- wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt;
-
- assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending
-
- always @( posedge Sys_Clk )
- begin
- D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout;
- INIT_B_reg <= WrFifo_Empty;
- end
-
- //----------------------------------------------------------------------------
-
-endmodule
-
-
-module main
- (
- // User clock ports
- Clkin_p,
- Clkin_m,
-
- // SelectMAP interface ports
- D, // Data bus
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK, // Local CCLK output
- gpleds,
- terminal
- );
-
- // User clock/reset ports
- input Clkin_p;
- input Clkin_m;
-
- // SelectMAP protocol ports
- inout [0:7] D;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
- output [6:1] gpleds;
-
-
- // Wires
- wire CCLK_int;
-
- wire [0:31] LoopData;
- wire [0:31] LoopDataW;
- wire LoopEmpty;
- wire LoopFull;
-
- wire [0:7] D_I;
- wire [0:7] D_O;
- wire [0:7] D_T;
-
- wire User_Clk;
- wire User_Rst;
-
- reg [6:1] gpleds_reg;
-
- // synthesis attribute tig of activate_r is yes;
- wire activate_r;
- // synthesis attribute tig of activate_a is yes;
- wire activate_a;
-
- wire [7:0] write_data;
- wire write_enable;
- wire write_full;
-
- wire [7:0] read_data;
- wire read_empty;
- wire [7:0] read_wire;
-
- reg [7:0] write_reg;
- reg [7:0] read_reg;
- wire read_enable;
- reg read_enable_;
- assign read_enable = read_enable_;
- inout [33:0] terminal;
-
- always @(posedge User_Clk) begin
- if (!read_enable && !read_empty) begin
- read_enable_ <= 1;
- end else begin
- read_enable_ <= 0;
- end
- end
- Maps_Bee2_Map0 map (.Clock(User_Clk),
- ._SW(1'b0),
- ._BTN(~read_enable_),
- .__TERMINAL_SynchronousLink_Pins(terminal));
-
-//synthesis attribute LOC of terminal is "AT13,AR13,AV13,AU13,AW13,AY13,AL15,AL14,AV15,AU15,AY14,AY15,AM16,AL16,AP16,AN16,AR16,AT16,AV16,AU16,AL18,AL17,AM17,AN17,AR17,AP17,AU17,AT17,AW16,AW17,AN18,AM18,AT18,AR18"
-
-
- // IO buffers
- OBUF obuf_cclk( .I( CCLK_int ),
- .O( CCLK )
- );
-
- IOBUF iobuf_d0( .I( D_O[0] ),
- .IO( D[0] ),
- .O( D_I[0] ),
- .T( D_T[0] )
- );
-
- IOBUF iobuf_d1( .I( D_O[1] ),
- .IO( D[1] ),
- .O( D_I[1] ),
- .T( D_T[1] )
- );
-
- IOBUF iobuf_d2( .I( D_O[2] ),
- .IO( D[2] ),
- .O( D_I[2] ),
- .T( D_T[2] )
- );
-
- IOBUF iobuf_d3( .I( D_O[3] ),
- .IO( D[3] ),
- .O( D_I[3] ),
- .T( D_T[3] )
- );
-
- IOBUF iobuf_d4( .I( D_O[4] ),
- .IO( D[4] ),
- .O( D_I[4] ),
- .T( D_T[4] )
- );
-
- IOBUF iobuf_d5( .I( D_O[5] ),
- .IO( D[5] ),
- .O( D_I[5] ),
- .T( D_T[5] )
- );
-
- IOBUF iobuf_d6( .I( D_O[6] ),
- .IO( D[6] ),
- .O( D_I[6] ),
- .T( D_T[6] )
- );
-
- IOBUF iobuf_d7( .I( D_O[7] ),
- .IO( D[7] ),
- .O( D_I[7] ),
- .T( D_T[7] )
- );
-
- // Clock buffer and reset
- IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
- .IB( Clkin_m ),
- .O( User_Clk )
- );
-
- wire [0:3] rst;
-
- FD rst0( .D( 1'b0 ),
- .Q( rst[0] ),
- .C( User_Clk )
- );
- defparam rst0.INIT = 1'b1;
-
- FD rst1( .D( rst[0] ),
- .Q( rst[1] ),
- .C( User_Clk )
- );
- defparam rst1.INIT = 1'b1;
-
- FD rst2( .D( rst[1] ),
- .Q( rst[2] ),
- .C( User_Clk )
- );
- defparam rst2.INIT = 1'b1;
-
- FD rst3( .D( rst[2] ),
- .Q( rst[3] ),
- .C( User_Clk )
- );
- defparam rst3.INIT = 1'b1;
-
- assign User_Rst = |rst;
-
-
- // FIFO module instantiation
- user_fifo test_fifo(
- .WrFifo_Din( write_data ),
- .WrFifo_WrEn( write_enable ),
- .WrFifo_Full( write_full ),
- .WrFifo_WrCnt( ),
- .RdFifo_Dout( read_data ),
- .RdFifo_RdEn( read_enable ),
- .RdFifo_Empty( read_empty ),
- .RdFifo_RdCnt( ),
- .User_Rst( User_Rst ),
- .User_Clk( User_Clk ),
- .Sys_Rst( User_Rst ),
- .Sys_Clk( User_Clk ),
- .D_I( D_I ),
- .D_O( D_O ),
- .D_T( D_T ),
- .RDWR_B( RDWR_B ),
- .CS_B( CS_B ),
- .INIT_B( INIT_B ),
- .CCLK( CCLK_int )
- );
-
-endmodule
+++ /dev/null
-`timescale 1ps / 1ps
-
-// Copyright (c) 2005-2006, Regents of the University of California
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-// - Neither the name of the University of California, Berkeley nor the
-// names of its contributors may be used to endorse or promote
-// products derived from this software without specific prior
-// written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-//----------------------------------------------------------------------------
-// user_fifo.v
-//----------------------------------------------------------------------------
-
-`timescale 1ps / 1ps
-
-module user_fifo
- (
- // FIFO interface ports
- WrFifo_Din, // Write FIFO data-in
- WrFifo_WrEn, // Write FIFO write enable
- WrFifo_Full, // Write FIFO full
- WrFifo_WrCnt, // Write FIFO write count
- RdFifo_Dout, // Read FIFO data-out
- RdFifo_RdEn, // Read FIFO read enable
- RdFifo_Empty, // Read FIFO empty
- RdFifo_RdCnt, // Read FIFO read count
- User_Rst, // User reset
- User_Clk, // User clock
- Sys_Rst, // System clock reset
- Sys_Clk, // 100MHz system clock for CCLK generation
-
- // SelectMAP interface ports
- D_I, // Data bus input
- D_O, // Data bus output
- D_T, // Data bus tristate enable
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK // CCLK output
- );
-
- // FIFO interface ports
- input [0:7] WrFifo_Din;
- input WrFifo_WrEn;
- output WrFifo_Full;
- output [0:7] WrFifo_WrCnt;
- output [0:7] RdFifo_Dout;
- input RdFifo_RdEn;
- output RdFifo_Empty;
- output [0:7] RdFifo_RdCnt;
- input User_Rst;
- input User_Clk;
- input Sys_Rst;
- input Sys_Clk;
-
- // SelectMAP protocol ports
- input [0:7] D_I;
- output [0:7] D_O;
- output [0:7] D_T;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
-
- // ____ __ _ _ _ _ //
- // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ //
- // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| //
- // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ //
- // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ //
- // //
-
- //----------------------------------------------------------------------------
- // Signal definitions
- //----------------------------------------------------------------------------
- // Write FIFO signals
- wire [0:7] WrFifo_Dout;
- wire WrFifo_Empty;
- wire WrFifo_RdEn;
- wire [0:7] WrFifo_RdCnt;
- wire [0:7] WrFifo_RdCnt_int;
- wire [0:7] WrFifo_WrCnt_int;
-
- // Read FIFO signals
- wire [0:7] RdFifo_Din;
- wire RdFifo_Full;
- wire RdFifo_WrEn;
- wire [0:7] RdFifo_WrCnt;
- wire [0:7] RdFifo_WrCnt_int;
- wire [0:7] RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // IO Registers
- //----------------------------------------------------------------------------
- reg CCLK;
-
- reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true;
- reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true;
- reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true;
- reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true;
- reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true;
-
- // Outputs
- assign D_O = D_O_reg;
- assign INIT_B = INIT_B_reg;
-
- // Inputs
- always @( posedge Sys_Clk )
- begin
- D_I_reg <= D_I;
- RDWR_B_reg <= RDWR_B;
- CS_B_reg <= CS_B;
- end
-
- //----------------------------------------------------------------------------
- // Generate CCLK and associated reset
- //----------------------------------------------------------------------------
- reg SYNC_done;
- reg SYNC_done_dly;
- reg CS_B_reg_dly;
-
- always @( posedge Sys_Clk )
- begin
- CS_B_reg_dly <= CS_B_reg;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done <= 1'b0;
- else if (RDWR_B_reg && ~CS_B_reg)
- SYNC_done <= 1'b1;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done_dly <= 1'b0;
- else
- SYNC_done_dly <= SYNC_done;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- CCLK <= 1'b0;
- else if (~CS_B_reg && CS_B_reg_dly && CCLK)
- CCLK <= 1'b1;
- else
- CCLK <= ~CCLK;
- end
-
- // _____ ___ _____ ___ //
- // | ___|_ _| ___/ _ \ ___ //
- // | |_ | || |_ | | | / __| //
- // | _| | || _|| |_| \__ \ //
- // |_| |___|_| \___/|___/ //
- // //
- // Write FIFO: The write is with respect to the user. The user writes data to this
- // FIFO and the control side of SelectMAP reads the data.
- //
- // Read FIFO: The read is with respect to the user. The user reads data sent from the
- // control side of SelectMAP.
- //
-
- //----------------------------------------------------------------------------
- // Read FIFO
- //----------------------------------------------------------------------------
- assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK;
- assign RdFifo_Din = D_I_reg;
-
- async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ),
- .dout( RdFifo_Dout ),
- .rd_clk( User_Clk ),
- .rd_en( RdFifo_RdEn ),
- .wr_clk( Sys_Clk ),
- .wr_en( RdFifo_WrEn ),
- .rst( User_Rst ),
- .empty( RdFifo_Empty ),
- .full( RdFifo_Full ),
- .rd_data_count( RdFifo_RdCnt_int ),
- .wr_data_count( RdFifo_WrCnt_int ) );
-
- assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int;
- assign RdFifo_RdCnt = RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // Write FIFO
- //----------------------------------------------------------------------------
- assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK;
-
- async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ),
- .dout( WrFifo_Dout ),
- .rd_clk( Sys_Clk ),
- .rd_en( WrFifo_RdEn ),
- .wr_clk( User_Clk ),
- .wr_en( WrFifo_WrEn ),
- .rst( User_Rst ),
- .empty( WrFifo_Empty ),
- .full( WrFifo_Full ),
- .rd_data_count( WrFifo_RdCnt_int ),
- .wr_data_count( WrFifo_WrCnt_int ) );
-
- assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int;
- assign WrFifo_RdCnt = WrFifo_RdCnt_int;
-
- // ____ _ _ __ __ _ ____ //
- // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ //
- // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | //
- // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ //
- // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| //
- // //
-
- //----------------------------------------------------------------------------
- // SelectMAP control outputs
- //----------------------------------------------------------------------------
- wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt;
-
- assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending
-
- always @( posedge Sys_Clk )
- begin
- D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout;
- INIT_B_reg <= WrFifo_Empty;
- end
-
- //----------------------------------------------------------------------------
-
-endmodule
-
-
-module main
- (
- // User clock ports
- Clkin_p,
- Clkin_m,
-
- // SelectMAP interface ports
- D, // Data bus
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK, // Local CCLK output
- gpleds,
- terminal
- );
-
- // User clock/reset ports
- input Clkin_p;
- input Clkin_m;
-
- // SelectMAP protocol ports
- inout [0:7] D;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
- output [6:1] gpleds;
-
-
- // Wires
- wire CCLK_int;
-
- wire [0:31] LoopData;
- wire [0:31] LoopDataW;
- wire LoopEmpty;
- wire LoopFull;
-
- wire [0:7] D_I;
- wire [0:7] D_O;
- wire [0:7] D_T;
-
- wire User_Clk;
- wire User_Rst;
-
- reg [6:1] gpleds_reg;
-
- // synthesis attribute tig of activate_r is yes;
- wire activate_r;
- // synthesis attribute tig of activate_a is yes;
- wire activate_a;
-
- wire [7:0] write_data;
- wire write_enable;
- wire write_full;
-
- wire [7:0] read_data;
- wire read_empty;
- wire [7:0] read_wire;
-
- reg [7:0] write_reg;
- reg [7:0] read_reg;
- wire read_enable;
- inout [33:0] terminal;
- wire [7:0] write_data_;
- assign write_data = write_data_ + 48;
-
- Maps_Bee2_Map1 map (.Clock(User_Clk),
- .SelectMapData(write_data_),
- .SelectMapWrite(write_enable),
- .__TERMINAL_SynchronousLink_Pins(terminal));
-
-//synthesis attribute LOC of terminal is "C15,L16,M16,J16,K16,H16,G16,E16,F16,M18,M17,L17,K17,H17,J17,F17,G17,D16,D17,K18,L18,G18,H18,E17,E18,C18,C17,L19,M19,J19,K19,G19,H19,E19"
-
-
- // IO buffers
- OBUF obuf_cclk( .I( CCLK_int ),
- .O( CCLK )
- );
-
- IOBUF iobuf_d0( .I( D_O[0] ),
- .IO( D[0] ),
- .O( D_I[0] ),
- .T( D_T[0] )
- );
-
- IOBUF iobuf_d1( .I( D_O[1] ),
- .IO( D[1] ),
- .O( D_I[1] ),
- .T( D_T[1] )
- );
-
- IOBUF iobuf_d2( .I( D_O[2] ),
- .IO( D[2] ),
- .O( D_I[2] ),
- .T( D_T[2] )
- );
-
- IOBUF iobuf_d3( .I( D_O[3] ),
- .IO( D[3] ),
- .O( D_I[3] ),
- .T( D_T[3] )
- );
-
- IOBUF iobuf_d4( .I( D_O[4] ),
- .IO( D[4] ),
- .O( D_I[4] ),
- .T( D_T[4] )
- );
-
- IOBUF iobuf_d5( .I( D_O[5] ),
- .IO( D[5] ),
- .O( D_I[5] ),
- .T( D_T[5] )
- );
-
- IOBUF iobuf_d6( .I( D_O[6] ),
- .IO( D[6] ),
- .O( D_I[6] ),
- .T( D_T[6] )
- );
-
- IOBUF iobuf_d7( .I( D_O[7] ),
- .IO( D[7] ),
- .O( D_I[7] ),
- .T( D_T[7] )
- );
-
- // Clock buffer and reset
- IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
- .IB( Clkin_m ),
- .O( User_Clk )
- );
-
- wire [0:3] rst;
-
- FD rst0( .D( 1'b0 ),
- .Q( rst[0] ),
- .C( User_Clk )
- );
- defparam rst0.INIT = 1'b1;
-
- FD rst1( .D( rst[0] ),
- .Q( rst[1] ),
- .C( User_Clk )
- );
- defparam rst1.INIT = 1'b1;
-
- FD rst2( .D( rst[1] ),
- .Q( rst[2] ),
- .C( User_Clk )
- );
- defparam rst2.INIT = 1'b1;
-
- FD rst3( .D( rst[2] ),
- .Q( rst[3] ),
- .C( User_Clk )
- );
- defparam rst3.INIT = 1'b1;
-
- assign User_Rst = |rst;
-
-
- // FIFO module instantiation
- user_fifo test_fifo(
- .WrFifo_Din( write_data ),
- .WrFifo_WrEn( write_enable ),
- .WrFifo_Full( write_full ),
- .WrFifo_WrCnt( ),
- .RdFifo_Dout( read_data ),
- .RdFifo_RdEn( read_enable ),
- .RdFifo_Empty( read_empty ),
- .RdFifo_RdCnt( ),
- .User_Rst( User_Rst ),
- .User_Clk( User_Clk ),
- .Sys_Rst( User_Rst ),
- .Sys_Clk( User_Clk ),
- .D_I( D_I ),
- .D_O( D_O ),
- .D_T( D_T ),
- .RDWR_B( RDWR_B ),
- .CS_B( CS_B ),
- .INIT_B( INIT_B ),
- .CCLK( CCLK_int )
- );
-
-endmodule
+++ /dev/null
-#!/usr/bin/perl
-
-`rm Map1.v`;
-`cp ../Map0.v .`;
-`cp ../main_map0.v main.v`;
-`make -f Makefile0`;
-`rm Map0.v`;
-`cp ../Map1.v .`;
-`cp ../main_map1.v main.v`;
-`make -f Makefile1`;
+++ /dev/null
-#!/usr/bin/perl
-
-
-$foo = 5;
-$f=0;
-while($f<$foo)
-{
-`echo "1234567890" > /dev/selectmap1`;
-`head -c11 /dev/selectmap2 >> transcript`;
-`echo '\n' >> transcript`;
-$f = $f+1;
-}
-
+++ /dev/null
-// megacz@cs.berkeley.edu, public domain
-
-module root(clk,
- read_empty, read_enable, read_data,
- write_full, write_enable, write_data);
-
- input clk;
- input read_empty;
- input write_full;
- output read_enable;
- output write_enable;
- input [7:0] read_data;
- output [7:0] write_data;
-
- reg read_enable_;
- assign read_enable = read_enable_;
- reg write_enable_;
- assign write_enable = write_enable_;
- reg [7:0] write_data_;
- assign write_data = write_data_;
-
- initial read_enable_ = 1;
- initial write_enable_ = 0;
-
- always @(posedge clk) begin
-
- // if there's stuff to read and room to write, read a byte,
- // increment it, and write it
- if (!read_enable_ && !write_enable_ && !read_empty && !write_full) begin
- read_enable_ <= 1;
- write_enable_ <= 1;
- write_data_ <= read_data + 1;
-
- // else do nothing
- end else begin
- read_enable_ <= 0;
- write_enable_ <= 0;
-
- end
-
- end
-
-endmodule
projects / fleet.git / commitdiff