ship: Dvi
== Ports ===========================================================
-data in: inX
-data in: inY
-data in: inData
+data in: inPixelX
+data in: inPixelY
+data in: inPixelValue
data in: inAddrRead
data in: inAddrWrite
.V_BP(31),
.HEIGHT_BITS(10),
.WIDTH_BITS(10),
- .DATA_DELAY(0)
+ .DATA_DELAY(1)
) my_vga_timing_generator (
.rst(rst),
.clk(pix_clk),
ODDR ODDR_dvi_d10 (dvi_d10, pix_clk, 1, dvi_red[6], dvi_green[2], ~data_valid_ext, 0);
ODDR ODDR_dvi_d11 (dvi_d11, pix_clk, 1, dvi_red[7], dvi_green[3], ~data_valid_ext, 0);
-
reg we;
reg [31:0] mem_out;
- wire [18:0] inAddr;
- wire [18:0] vga_pixel_addr_;
- reg [18:0] vga_pixel_addr;
- reg [18:0] last_vga_pixel_addr;
-
-reg write_enable;
-reg oe;
-reg [2:0] wait_cycles;
-reg was_write;
-reg was_video;
-reg [37:0] addr;
-wire [31:0] data_out;
-reg [37:0] out_d;
-
-assign out_d_ = out_d;
-
-assign sram_flash_a0 = addr[0];
-assign sram_flash_a1 = addr[1];
-assign sram_flash_a2 = addr[2];
-assign sram_flash_a3 = addr[3];
-assign sram_flash_a4 = addr[4];
-assign sram_flash_a5 = addr[5];
-assign sram_flash_a6 = addr[6];
-assign sram_flash_a7 = addr[7];
-assign sram_flash_a8 = addr[8];
-assign sram_flash_a9 = addr[9];
-assign sram_flash_a10 = addr[10];
-assign sram_flash_a11 = addr[11];
-assign sram_flash_a12 = addr[12];
-assign sram_flash_a13 = addr[13];
-assign sram_flash_a14 = addr[14];
-assign sram_flash_a15 = addr[15];
-assign sram_flash_a16 = addr[16];
-assign sram_flash_a17 = addr[17];
-assign sram_flash_a18 = addr[18];
-assign sram_flash_a19 = addr[19];
-assign sram_flash_a20 = addr[20];
-assign sram_flash_a21 = addr[21];
-
-assign data_out[0] = sram_flash_d0; assign sram_flash_d0 = oe ? 1'bz : inDataWrite_d[0];
-assign data_out[1] = sram_flash_d1; assign sram_flash_d1 = oe ? 1'bz : inDataWrite_d[1];
-assign data_out[2] = sram_flash_d2; assign sram_flash_d2 = oe ? 1'bz : inDataWrite_d[2];
-assign data_out[3] = sram_flash_d3; assign sram_flash_d3 = oe ? 1'bz : inDataWrite_d[3];
-assign data_out[4] = sram_flash_d4; assign sram_flash_d4 = oe ? 1'bz : inDataWrite_d[4];
-assign data_out[5] = sram_flash_d5; assign sram_flash_d5 = oe ? 1'bz : inDataWrite_d[5];
-assign data_out[6] = sram_flash_d6; assign sram_flash_d6 = oe ? 1'bz : inDataWrite_d[6];
-assign data_out[7] = sram_flash_d7; assign sram_flash_d7 = oe ? 1'bz : inDataWrite_d[7];
-assign data_out[8] = sram_flash_d8; assign sram_flash_d8 = oe ? 1'bz : inDataWrite_d[8];
-assign data_out[9] = sram_flash_d9; assign sram_flash_d9 = oe ? 1'bz : inDataWrite_d[9];
-assign data_out[10] = sram_flash_d10; assign sram_flash_d10 = oe ? 1'bz : inDataWrite_d[10];
-assign data_out[11] = sram_flash_d11; assign sram_flash_d11 = oe ? 1'bz : inDataWrite_d[11];
-assign data_out[12] = sram_flash_d12; assign sram_flash_d12 = oe ? 1'bz : inDataWrite_d[12];
-assign data_out[13] = sram_flash_d13; assign sram_flash_d13 = oe ? 1'bz : inDataWrite_d[13];
-assign data_out[14] = sram_flash_d14; assign sram_flash_d14 = oe ? 1'bz : inDataWrite_d[14];
-assign data_out[15] = sram_flash_d15; assign sram_flash_d15 = oe ? 1'bz : inDataWrite_d[15];
-assign data_out[16] = sram_d16; assign sram_d16 = oe ? 1'bz : inDataWrite_d[16];
-assign data_out[17] = sram_d17; assign sram_d17 = oe ? 1'bz : inDataWrite_d[17];
-assign data_out[18] = sram_d18; assign sram_d18 = oe ? 1'bz : inDataWrite_d[18];
-assign data_out[19] = sram_d19; assign sram_d19 = oe ? 1'bz : inDataWrite_d[19];
-assign data_out[20] = sram_d20; assign sram_d20 = oe ? 1'bz : inDataWrite_d[20];
-assign data_out[21] = sram_d21; assign sram_d21 = oe ? 1'bz : inDataWrite_d[21];
-assign data_out[22] = sram_d22; assign sram_d22 = oe ? 1'bz : inDataWrite_d[22];
-assign data_out[23] = sram_d23; assign sram_d23 = oe ? 1'bz : inDataWrite_d[23];
-assign data_out[24] = sram_d24; assign sram_d24 = oe ? 1'bz : inDataWrite_d[24];
-assign data_out[25] = sram_d25; assign sram_d25 = oe ? 1'bz : inDataWrite_d[25];
-assign data_out[26] = sram_d26; assign sram_d26 = oe ? 1'bz : inDataWrite_d[26];
-assign data_out[27] = sram_d27; assign sram_d27 = oe ? 1'bz : inDataWrite_d[27];
-assign data_out[28] = sram_d28; assign sram_d28 = oe ? 1'bz : inDataWrite_d[28];
-assign data_out[29] = sram_d29; assign sram_d29 = oe ? 1'bz : inDataWrite_d[29];
-assign data_out[30] = sram_d30; assign sram_d30 = oe ? 1'bz : inDataWrite_d[30];
-assign data_out[31] = sram_d31; assign sram_d31 = oe ? 1'bz : inDataWrite_d[31];
-
-assign sram_mode = 0;
-assign sram_clk = clk;
-assign sram_bw0 = ~write_enable;
-assign sram_bw1 = ~write_enable;
-assign sram_bw2 = ~write_enable;
-assign sram_bw3 = ~write_enable;
-assign sram_flash_we_b = ~write_enable;
-assign sram_adv_ld_b = 0;
-assign sram_cs_b = 0;
-assign sram_oe_b = ~oe;
-
- assign inAddr = inX_d + { inY_d[8:0], 7'b0000000 } + { inY_d[8:0], 10'b0000000000 };
- assign vga_pixel_addr_ = x_coord + { y_coord[8:0], 7'b0000000 } + { y_coord[8:0], 10'b0000000000 };
- assign dvi_red = mem_out[23:16];
- assign dvi_green = mem_out[15:8];
- assign dvi_blue = mem_out[7:0];
-
- wire [2:0] mem_out_old;
- vram vram(clk, ~rst, we,
- inAddr[18:0],
- vga_pixel_addr,
- inData_d, ,
- mem_out_old);
+ wire [20:0] inAddr;
+ wire [20:0] vga_pixel_addr_;
+ reg [20:0] vga_pixel_addr;
+ reg [20:0] last_vga_pixel_addr;
+
+ reg write_enable;
+ reg oe;
+ reg [3:0] wait_until_read;
+ reg [3:0] wait_until_write;
+ reg [3:0] wait_until_video;
+ reg [37:0] addr;
+ wire [31:0] data_out;
+ reg [37:0] out_d;
+ reg [37:0] writeData;
+
+ reg use_addr;
+
+ assign out_d_ = out_d;
+
+ assign sram_flash_a0 = use_addr ? addr[0] : 0;
+ assign sram_flash_a1 = use_addr ? addr[1] : vga_pixel_addr[0];
+ assign sram_flash_a2 = use_addr ? addr[2] : vga_pixel_addr[1];
+ assign sram_flash_a3 = use_addr ? addr[3] : vga_pixel_addr[2];
+ assign sram_flash_a4 = use_addr ? addr[4] : vga_pixel_addr[3];
+ assign sram_flash_a5 = use_addr ? addr[5] : vga_pixel_addr[4];
+ assign sram_flash_a6 = use_addr ? addr[6] : vga_pixel_addr[5];
+ assign sram_flash_a7 = use_addr ? addr[7] : vga_pixel_addr[6];
+ assign sram_flash_a8 = use_addr ? addr[8] : vga_pixel_addr[7];
+ assign sram_flash_a9 = use_addr ? addr[9] : vga_pixel_addr[8];
+ assign sram_flash_a10 = use_addr ? addr[10] : vga_pixel_addr[9];
+ assign sram_flash_a11 = use_addr ? addr[11] : vga_pixel_addr[10];
+ assign sram_flash_a12 = use_addr ? addr[12] : vga_pixel_addr[11];
+ assign sram_flash_a13 = use_addr ? addr[13] : vga_pixel_addr[12];
+ assign sram_flash_a14 = use_addr ? addr[14] : vga_pixel_addr[13];
+ assign sram_flash_a15 = use_addr ? addr[15] : vga_pixel_addr[14];
+ assign sram_flash_a16 = use_addr ? addr[16] : vga_pixel_addr[15];
+ assign sram_flash_a17 = use_addr ? addr[17] : vga_pixel_addr[16];
+ assign sram_flash_a18 = use_addr ? addr[18] : vga_pixel_addr[17];
+ assign sram_flash_a19 = use_addr ? addr[19] : vga_pixel_addr[18];
+ assign sram_flash_a20 = use_addr ? addr[20] : vga_pixel_addr[19];
+ assign sram_flash_a21 = use_addr ? addr[21] : vga_pixel_addr[20];
+
+ assign data_out[0] = sram_flash_d0; assign sram_flash_d0 = oe ? 1'bz : writeData[0];
+ assign data_out[1] = sram_flash_d1; assign sram_flash_d1 = oe ? 1'bz : writeData[1];
+ assign data_out[2] = sram_flash_d2; assign sram_flash_d2 = oe ? 1'bz : writeData[2];
+ assign data_out[3] = sram_flash_d3; assign sram_flash_d3 = oe ? 1'bz : writeData[3];
+ assign data_out[4] = sram_flash_d4; assign sram_flash_d4 = oe ? 1'bz : writeData[4];
+ assign data_out[5] = sram_flash_d5; assign sram_flash_d5 = oe ? 1'bz : writeData[5];
+ assign data_out[6] = sram_flash_d6; assign sram_flash_d6 = oe ? 1'bz : writeData[6];
+ assign data_out[7] = sram_flash_d7; assign sram_flash_d7 = oe ? 1'bz : writeData[7];
+ assign data_out[8] = sram_flash_d8; assign sram_flash_d8 = oe ? 1'bz : writeData[8];
+ assign data_out[9] = sram_flash_d9; assign sram_flash_d9 = oe ? 1'bz : writeData[9];
+ assign data_out[10] = sram_flash_d10; assign sram_flash_d10 = oe ? 1'bz : writeData[10];
+ assign data_out[11] = sram_flash_d11; assign sram_flash_d11 = oe ? 1'bz : writeData[11];
+ assign data_out[12] = sram_flash_d12; assign sram_flash_d12 = oe ? 1'bz : writeData[12];
+ assign data_out[13] = sram_flash_d13; assign sram_flash_d13 = oe ? 1'bz : writeData[13];
+ assign data_out[14] = sram_flash_d14; assign sram_flash_d14 = oe ? 1'bz : writeData[14];
+ assign data_out[15] = sram_flash_d15; assign sram_flash_d15 = oe ? 1'bz : writeData[15];
+ assign data_out[16] = sram_d16; assign sram_d16 = oe ? 1'bz : writeData[16];
+ assign data_out[17] = sram_d17; assign sram_d17 = oe ? 1'bz : writeData[17];
+ assign data_out[18] = sram_d18; assign sram_d18 = oe ? 1'bz : writeData[18];
+ assign data_out[19] = sram_d19; assign sram_d19 = oe ? 1'bz : writeData[19];
+ assign data_out[20] = sram_d20; assign sram_d20 = oe ? 1'bz : writeData[20];
+ assign data_out[21] = sram_d21; assign sram_d21 = oe ? 1'bz : writeData[21];
+ assign data_out[22] = sram_d22; assign sram_d22 = oe ? 1'bz : writeData[22];
+ assign data_out[23] = sram_d23; assign sram_d23 = oe ? 1'bz : writeData[23];
+ assign data_out[24] = sram_d24; assign sram_d24 = oe ? 1'bz : writeData[24];
+ assign data_out[25] = sram_d25; assign sram_d25 = oe ? 1'bz : writeData[25];
+ assign data_out[26] = sram_d26; assign sram_d26 = oe ? 1'bz : writeData[26];
+ assign data_out[27] = sram_d27; assign sram_d27 = oe ? 1'bz : writeData[27];
+ assign data_out[28] = sram_d28; assign sram_d28 = oe ? 1'bz : writeData[28];
+ assign data_out[29] = sram_d29; assign sram_d29 = oe ? 1'bz : writeData[29];
+ assign data_out[30] = sram_d30; assign sram_d30 = oe ? 1'bz : writeData[30];
+ assign data_out[31] = sram_d31; assign sram_d31 = oe ? 1'bz : writeData[31];
+
+ assign sram_mode = 0;
+ assign sram_clk = clk;
+ assign sram_bw0 = ~write_enable;
+ assign sram_bw1 = ~write_enable;
+ assign sram_bw2 = ~write_enable;
+ assign sram_bw3 = ~write_enable;
+ assign sram_flash_we_b = ~write_enable;
+ assign sram_adv_ld_b = 0;
+ assign sram_cs_b = 0;
+ assign sram_oe_b = ~oe;
+
+ // Framebuffer is 548x478 -- yeah, I know that's completely weird.
+
+ wire on_screen;
+ assign on_screen = (x_coord >= 48) && (x_coord < 592);
+ wire [9:0] adjusted_x_coord;
+ assign adjusted_x_coord = x_coord - 48;
+
+ assign inAddr = inPixelX_d[20:0]
+ + { 7'b0000000, inPixelY_d[8:0], 5'b00000 }
+ + { 3'b000, inPixelY_d[8:0], 9'b0000000000 };
+ assign vga_pixel_addr_ = { 11'b00000000000, adjusted_x_coord }
+ + { 7'b0000000, y_coord[8:0], 5'b00000 }
+ + { 3'b000, y_coord[8:0], 9'b0000000000 };
+
+ assign dvi_red = on_screen ? mem_out[23:16] : 0;
+ assign dvi_green = on_screen ? mem_out[15:8] : 0;
+ assign dvi_blue = on_screen ? mem_out[7:0] : 0;
always @(posedge pix_clk) begin
vga_pixel_addr <= vga_pixel_addr_;
end
-always @(posedge clk) begin
- if (rst) begin
- `reset
- wait_cycles <= 0;
-
- end else begin
- `cleanup
+ wire idle;
+ assign idle = (wait_until_write==0 && wait_until_read==0 && wait_until_video==0);
+
+ always @(posedge clk) begin
+ if (rst) begin
+ `reset
+ wait_until_read <= 0;
+ wait_until_video <= 0;
+ wait_until_write <= 0;
+ use_addr <= 0;
+
+ end else begin
+ `cleanup
+
+ write_enable <= 0;
+ oe <= 1;
- write_enable <= 0;
- oe <= 1;
- if (wait_cycles == 1) begin
- if (was_video) begin
- mem_out <= data_out;
- end else if (was_write) begin
- out_d <= { 1'b1, 37'b0 };
- `fill_out
- `drain_inDataWrite
- `drain_inAddrWrite
+ if (wait_until_write == 1) begin
+ wait_until_write <= 0;
oe <= 0;
- end else begin
+ use_addr <= 0;
+ end else if (wait_until_write != 0) begin
+ wait_until_write <= wait_until_write-1;
+ end
+
+ if (wait_until_read == 1) begin
+ wait_until_read <= 0;
out_d <= { 1'b0, data_out };
`fill_out
`drain_inAddrRead
+ use_addr <= 0;
+ end else if (wait_until_read != 0) begin
+ wait_until_read <= wait_until_read-1;
end
- wait_cycles <= 0;
-
- end else if (wait_cycles != 0) begin
- wait_cycles <= wait_cycles-1;
-
- end else if (`inAddrWrite_full && `inDataWrite_full) begin
- write_enable <= 1;
- was_write <= 1;
- was_video <= 0;
- wait_cycles <= 1;
- addr <= { inAddrWrite_d, 1'b0 };
-
- end else if (`inAddrRead_full) begin
- write_enable <= 0;
- was_write <= 0;
- was_video <= 0;
- wait_cycles <= 3;
- addr <= { inAddrRead_d, 1'b0 };
-
- end else if (last_vga_pixel_addr != vga_pixel_addr) begin
- write_enable <= 0;
- was_write <= 0;
- was_video <= 1;
- wait_cycles <= 3;
- addr <= { vga_pixel_addr, 1'b0 };
- last_vga_pixel_addr <= vga_pixel_addr;
- end
- if (`inX_full && `inY_full && `inData_full) begin
- we <= 1;
- `drain_inX
- `drain_inY
- `drain_inData
- end else begin
- we <= 0;
- end
+ if (wait_until_video == 1) begin
+ wait_until_video <= 0;
+ mem_out <= data_out;
+ end else if (wait_until_video != 0) begin
+ wait_until_video <= wait_until_video-1;
+ end
+
+ if (`inAddrWrite_full && `inDataWrite_full && idle && `out_empty) begin
+ write_enable <= 1;
+ wait_until_write <= 1;
+ addr <= { inAddrWrite_d, 1'b0 };
+ writeData <= inDataWrite_d;
+ out_d <= { 1'b1, 37'b0 };
+ use_addr <= 1;
+ `fill_out
+ `drain_inDataWrite
+ `drain_inAddrWrite
+
+ end else if (`inPixelX_full && `inPixelY_full && `inPixelValue_full && idle) begin
+ `drain_inPixelX
+ `drain_inPixelY
+ `drain_inPixelValue
+ write_enable <= 1;
+ wait_until_write <= 1;
+ addr <= { inAddr, 1'b0 };
+ writeData <= inPixelValue_d;
+ use_addr <= 1;
+
+ end else if (`inAddrRead_full && idle && `out_empty) begin
+ // next cycle (wait_until_read==3) will assert the address for the request
+ // cycle after that (wait_until_read==2) is the gap
+ // cycle after that (wait_until_read==1) will have the valid data being asserted back
+ // unfortunately, I seem to get errors unless I wait for an EXTRA cycle on top of this.
+// wait_until_read <= 3;
+ wait_until_read <= 4;
+ addr <= { inAddrRead_d, 1'b0 };
+ use_addr <= 1;
+
+ end else if (last_vga_pixel_addr != vga_pixel_addr && idle && on_screen) begin
+ // wait_until_video can't be more than 3, because (3+1) is the ratio of the pixel clock to the host clock
+ wait_until_video <= 3;
+ addr <= { vga_pixel_addr, 1'b0 };
+ last_vga_pixel_addr <= vga_pixel_addr;
+ end
+
+ end
end
-end
== UCF ===============================================================
#ship debug : Debug
#ship video : Dvi
-video.inX:
+video.inPixelX:
set word=0;
deliver;
send token to debug.in;
-video.inY:
+video.inPixelY:
set word=0;
deliver;
send token to debug.in;
-video.inData:
+video.inPixelValue:
set word=0;
deliver;
send token to debug.in;
projects / fleet.git / commitdiff