2 -- squeese functions for the graph allocator
25 EABase(..), EAIndex(..), addrModeRegs,
27 eax, ebx, ecx, edx, esi, edi, ebp, esp,
28 fake0, fake1, fake2, fake3, fake4, fake5,
30 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
31 r8, r9, r10, r11, r12, r13, r14, r15,
32 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
33 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
43 get_GlobalReg_reg_or_addr,
49 #include "nativeGen/NCG.h"
50 #include "HsVersions.h"
53 # define STOLEN_X86_REGS 4
54 -- HACK: go for the max
57 #include "../includes/MachRegs.h"
62 import CgUtils ( get_GlobalReg_addr )
65 import CLabel ( CLabel )
67 import Outputable ( panic )
68 import qualified Outputable
73 #if defined(i386_TARGET_ARCH) || defined(x86_64_TARGET_ARCH)
78 -- | regSqueeze_class reg
79 -- Calculuate the maximum number of register colors that could be
80 -- denied to a node of this class due to having this reg
83 {-# INLINE virtualRegSqueeze #-}
84 virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt
86 virtualRegSqueeze cls vr
90 VirtualRegI{} -> _ILIT(1)
91 VirtualRegHi{} -> _ILIT(1)
92 VirtualRegD{} -> _ILIT(0)
93 VirtualRegF{} -> _ILIT(0)
95 -- We don't use floats on this arch, but we can't
96 -- return error because the return type is unboxed...
99 VirtualRegI{} -> _ILIT(0)
100 VirtualRegHi{} -> _ILIT(0)
101 VirtualRegD{} -> _ILIT(0)
102 VirtualRegF{} -> _ILIT(0)
106 VirtualRegI{} -> _ILIT(0)
107 VirtualRegHi{} -> _ILIT(0)
108 VirtualRegD{} -> _ILIT(1)
109 VirtualRegF{} -> _ILIT(0)
111 realRegSqueeze :: RegClass -> RealReg -> FastInt
113 #if defined(i386_TARGET_ARCH)
114 {-# INLINE realRegSqueeze #-}
115 realRegSqueeze cls rr
120 | regNo < 8 -> _ILIT(1) -- first fp reg is 8
121 | otherwise -> _ILIT(0)
123 RealRegPair{} -> _ILIT(0)
125 -- We don't use floats on this arch, but we can't
126 -- return error because the return type is unboxed...
130 | regNo < 8 -> _ILIT(0)
131 | otherwise -> _ILIT(0)
133 RealRegPair{} -> _ILIT(0)
138 | regNo < 8 -> _ILIT(0)
139 | otherwise -> _ILIT(1)
141 RealRegPair{} -> _ILIT(0)
143 #elif defined(x86_64_TARGET_ARCH)
144 realRegSqueeze cls rr
149 | regNo < 16 -> _ILIT(1) -- first xmm reg is 16
150 | otherwise -> _ILIT(0)
152 RealRegPair{} -> _ILIT(0)
154 -- We don't use floats on this arch, but we can't
155 -- return error because the return type is unboxed...
159 | regNo < 16 -> _ILIT(0)
160 | otherwise -> _ILIT(0)
162 RealRegPair{} -> _ILIT(0)
167 | regNo < 16 -> _ILIT(0)
168 | otherwise -> _ILIT(1)
170 RealRegPair{} -> _ILIT(0)
173 realRegSqueeze _ _ = _ILIT(0)
178 -- -----------------------------------------------------------------------------
183 | ImmInteger Integer -- Sigh.
184 | ImmCLbl CLabel -- AbstractC Label (with baggage)
185 | ImmLit Doc -- Simple string
186 | ImmIndex CLabel Int
189 | ImmConstantSum Imm Imm
190 | ImmConstantDiff Imm Imm
193 strImmLit :: String -> Imm
194 strImmLit s = ImmLit (text s)
197 litToImm :: CmmLit -> Imm
198 litToImm (CmmInt i w) = ImmInteger (narrowS w i)
199 -- narrow to the width: a CmmInt might be out of
200 -- range, but we assume that ImmInteger only contains
201 -- in-range values. A signed value should be fine here.
202 litToImm (CmmFloat f W32) = ImmFloat f
203 litToImm (CmmFloat f W64) = ImmDouble f
204 litToImm (CmmLabel l) = ImmCLbl l
205 litToImm (CmmLabelOff l off) = ImmIndex l off
206 litToImm (CmmLabelDiffOff l1 l2 off)
208 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
210 litToImm (CmmBlock id) = ImmCLbl (infoTblLbl id)
211 litToImm _ = panic "X86.Regs.litToImm: no match"
213 -- addressing modes ------------------------------------------------------------
216 = AddrBaseIndex EABase EAIndex Displacement
219 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
220 data EAIndex = EAIndexNone | EAIndex Reg Int
221 type Displacement = Imm
224 addrOffset :: AddrMode -> Int -> Maybe AddrMode
227 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
229 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
230 AddrBaseIndex r i (ImmInteger n)
231 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
233 AddrBaseIndex r i (ImmCLbl lbl)
234 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
236 AddrBaseIndex r i (ImmIndex lbl ix)
237 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
239 _ -> Nothing -- in theory, shouldn't happen
242 addrModeRegs :: AddrMode -> [Reg]
243 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
245 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
246 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
250 -- registers -------------------------------------------------------------------
252 -- @spRel@ gives us a stack relative addressing mode for volatile
253 -- temporaries and for excess call arguments. @fpRel@, where
254 -- applicable, is the same but for the frame pointer.
257 spRel :: Int -- ^ desired stack offset in words, positive or negative
261 spRel n = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
263 #elif x86_64_TARGET_ARCH
264 spRel n = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
267 spRel _ = panic "X86.Regs.spRel: not defined for this architecture"
272 -- argRegs is the set of regs which are read for an n-argument call to C.
273 -- For archs which pass all args on the stack (x86), is empty.
274 -- Sparc passes up to the first 6 args in regs.
275 -- Dunno about Alpha.
276 argRegs :: RegNo -> [Reg]
277 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
283 -- | The complete set of machine registers.
284 allMachRegNos :: [RegNo]
287 allMachRegNos = [0..13]
289 #elif x86_64_TARGET_ARCH
290 allMachRegNos = [0..31]
293 allMachRegNos = panic "X86.Regs.callClobberedRegs: not defined for this architecture"
298 -- | Take the class of a register.
299 {-# INLINE classOfRealReg #-}
300 classOfRealReg :: RealReg -> RegClass
303 -- On x86, we might want to have an 8-bit RegClass, which would
304 -- contain just regs 1-4 (the others don't have 8-bit versions).
305 -- However, we can get away without this at the moment because the
306 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
309 RealRegSingle i -> if i < 8 then RcInteger else RcDouble
310 RealRegPair{} -> panic "X86.Regs.classOfRealReg: RegPairs on this arch"
312 #elif x86_64_TARGET_ARCH
313 -- On x86, we might want to have an 8-bit RegClass, which would
314 -- contain just regs 1-4 (the others don't have 8-bit versions).
315 -- However, we can get away without this at the moment because the
316 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
319 RealRegSingle i -> if i < 16 then RcInteger else RcDouble
320 RealRegPair{} -> panic "X86.Regs.classOfRealReg: RegPairs on this arch"
323 classOfRealReg _ = panic "X86.Regs.regClass: not defined for this architecture"
328 -- | Get the name of the register with this number.
329 showReg :: RegNo -> String
333 = if n >= 0 && n < 14
335 else "%unknown_x86_real_reg_" ++ show n
339 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
340 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
342 #elif x86_64_TARGET_ARCH
344 | n >= 16 = "%xmm" ++ show (n-16)
345 | n >= 8 = "%r" ++ show n
346 | otherwise = regNames !! n
350 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
353 showReg _ = panic "X86.Regs.showReg: not defined for this architecture"
360 -- machine specific ------------------------------------------------------------
364 Intel x86 architecture:
365 - All registers except 7 (esp) are available for use.
366 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
367 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
368 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
369 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
370 fp registers, and 3-operand insns for them, and we translate this into
371 real stack-based x86 fp code after register allocation.
373 The fp registers are all Double registers; we don't have any RcFloat class
374 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
378 fake0, fake1, fake2, fake3, fake4, fake5,
379 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
399 AMD x86_64 architecture:
400 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
401 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
402 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
406 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
407 r8, r9, r10, r11, r12, r13, r14, r15,
408 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
409 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
444 allFPArgRegs :: [Reg]
445 allFPArgRegs = map regSingle [16 .. 23]
447 ripRel :: Displacement -> AddrMode
448 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
451 -- so we can re-use some x86 code:
464 xmm n = regSingle (16+n)
469 -- horror show -----------------------------------------------------------------
470 freeReg :: RegNo -> FastBool
471 globalRegMaybe :: GlobalReg -> Maybe RealReg
473 callClobberedRegs :: [Reg]
475 #if defined(i386_TARGET_ARCH) || defined(x86_64_TARGET_ARCH)
494 #if x86_64_TARGET_ARCH
532 freeReg esp = fastBool False -- %esp is the C stack pointer
535 #if x86_64_TARGET_ARCH
536 freeReg rsp = fastBool False -- %rsp is the C stack pointer
540 freeReg REG_Base = fastBool False
543 freeReg REG_R1 = fastBool False
546 freeReg REG_R2 = fastBool False
549 freeReg REG_R3 = fastBool False
552 freeReg REG_R4 = fastBool False
555 freeReg REG_R5 = fastBool False
558 freeReg REG_R6 = fastBool False
561 freeReg REG_R7 = fastBool False
564 freeReg REG_R8 = fastBool False
567 freeReg REG_F1 = fastBool False
570 freeReg REG_F2 = fastBool False
573 freeReg REG_F3 = fastBool False
576 freeReg REG_F4 = fastBool False
579 freeReg REG_D1 = fastBool False
582 freeReg REG_D2 = fastBool False
585 freeReg REG_Sp = fastBool False
588 freeReg REG_Su = fastBool False
591 freeReg REG_SpLim = fastBool False
594 freeReg REG_Hp = fastBool False
597 freeReg REG_HpLim = fastBool False
599 freeReg _ = fastBool True
602 -- | Returns 'Nothing' if this global register is not stored
603 -- in a real machine register, otherwise returns @'Just' reg@, where
604 -- reg is the machine register it is stored in.
607 globalRegMaybe BaseReg = Just (RealRegSingle REG_Base)
610 globalRegMaybe (VanillaReg 1 _) = Just (RealRegSingle REG_R1)
613 globalRegMaybe (VanillaReg 2 _) = Just (RealRegSingle REG_R2)
616 globalRegMaybe (VanillaReg 3 _) = Just (RealRegSingle REG_R3)
619 globalRegMaybe (VanillaReg 4 _) = Just (RealRegSingle REG_R4)
622 globalRegMaybe (VanillaReg 5 _) = Just (RealRegSingle REG_R5)
625 globalRegMaybe (VanillaReg 6 _) = Just (RealRegSingle REG_R6)
628 globalRegMaybe (VanillaReg 7 _) = Just (RealRegSingle REG_R7)
631 globalRegMaybe (VanillaReg 8 _) = Just (RealRegSingle REG_R8)
634 globalRegMaybe (VanillaReg 9 _) = Just (RealRegSingle REG_R9)
637 globalRegMaybe (VanillaReg 10 _) = Just (RealRegSingle REG_R10)
640 globalRegMaybe (FloatReg 1) = Just (RealRegSingle REG_F1)
643 globalRegMaybe (FloatReg 2) = Just (RealRegSingle REG_F2)
646 globalRegMaybe (FloatReg 3) = Just (RealRegSingle REG_F3)
649 globalRegMaybe (FloatReg 4) = Just (RealRegSingle REG_F4)
652 globalRegMaybe (DoubleReg 1) = Just (RealRegSingle REG_D1)
655 globalRegMaybe (DoubleReg 2) = Just (RealRegSingle REG_D2)
658 globalRegMaybe Sp = Just (RealRegSingle REG_Sp)
661 globalRegMaybe (LongReg 1) = Just (RealRegSingle REG_Lng1)
664 globalRegMaybe (LongReg 2) = Just (RealRegSingle REG_Lng2)
667 globalRegMaybe SpLim = Just (RealRegSingle REG_SpLim)
670 globalRegMaybe Hp = Just (RealRegSingle REG_Hp)
673 globalRegMaybe HpLim = Just (RealRegSingle REG_HpLim)
675 #ifdef REG_CurrentTSO
676 globalRegMaybe CurrentTSO = Just (RealRegSingle REG_CurrentTSO)
678 #ifdef REG_CurrentNursery
679 globalRegMaybe CurrentNursery = Just (RealRegSingle REG_CurrentNursery)
681 globalRegMaybe _ = Nothing
686 allArgRegs = panic "X86.Regs.allArgRegs: should not be used!"
688 #elif x86_64_TARGET_ARCH
689 allArgRegs = map regSingle [rdi,rsi,rdx,rcx,r8,r9]
692 allArgRegs = panic "X86.Regs.allArgRegs: not defined for this architecture"
696 -- | these are the regs which we cannot assume stay alive over a C call.
699 -- caller-saves registers
701 = map regSingle [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
703 #elif x86_64_TARGET_ARCH
704 -- all xmm regs are caller-saves
705 -- caller-saves registers
707 = map regSingle ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
711 = panic "X86.Regs.callClobberedRegs: not defined for this architecture"
714 #else /* i386_TARGET_ARCH || x86_64_TARGET_ARCH */
719 globalRegMaybe _ = panic "X86.Regs.globalRegMaybe: not defined"
721 allArgRegs = panic "X86.Regs.globalRegMaybe: not defined"
722 callClobberedRegs = panic "X86.Regs.globalRegMaybe: not defined"
727 -- We map STG registers onto appropriate CmmExprs. Either they map
728 -- to real machine registers or stored as offsets from BaseReg. Given
729 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
730 -- register it is in, on this platform, or a CmmExpr denoting the
731 -- address in the register table holding it.
732 -- (See also get_GlobalReg_addr in CgUtils.)
734 get_GlobalReg_reg_or_addr :: GlobalReg -> Either RealReg CmmExpr
735 get_GlobalReg_reg_or_addr mid
736 = case globalRegMaybe mid of
738 Nothing -> Right (get_GlobalReg_addr mid)
741 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
742 -- i.e., these are the regs for which we are prepared to allow the
743 -- register allocator to attempt to map VRegs to.
744 allocatableRegs :: [RealReg]
746 = let isFree i = isFastTrue (freeReg i)
747 in map RealRegSingle $ filter isFree allMachRegNos