import Size
import RegClass
import Reg
+import TargetReg
import Platform
-- Our intermediate code:
getRegisterReg :: CmmReg -> Reg
getRegisterReg (CmmLocal (LocalReg u pk))
- = mkVReg u (cmmTypeSize pk)
+ = RegVirtual $ mkVirtualReg u (cmmTypeSize pk)
getRegisterReg (CmmGlobal mid)
= case get_GlobalReg_reg_or_addr mid of
- Left reg@(RegReal _) -> reg
+ Left reg -> reg
_other -> pprPanic "getRegisterReg-memory" (ppr $ CmmGlobal mid)
-- By this stage, the only MagicIds remaining should be the
-- ones which map to a real machine register on this
assignReg_I64Code (CmmLocal (LocalReg u_dst pk)) valueTree = do
ChildCode64 vcode r_src_lo <- iselExpr64 valueTree
let
- r_dst_lo = mkVReg u_dst II32
+ r_dst_lo = RegVirtual $ mkVirtualReg u_dst II32
r_dst_hi = getHiVRegFromLo r_dst_lo
r_src_hi = getHiVRegFromLo r_src_lo
mov_lo = MR r_dst_lo r_src_lo
rlo
iselExpr64 (CmmReg (CmmLocal (LocalReg vu ty))) | isWord64 ty
- = return (ChildCode64 nilOL (mkVReg vu II32))
+ = return (ChildCode64 nilOL (RegVirtual $ mkVirtualReg vu II32))
iselExpr64 (CmmLit (CmmInt i _)) = do
(rlo,rhi) <- getNewRegPairNat II32
| not (isWord64 pk)
= do
Amode addr addr_code <- getAmode mem
- let code dst = ASSERT((regClass dst == RcDouble) == isFloatType pk)
+ let code dst = ASSERT((targetClassOfReg dst == RcDouble) == isFloatType pk)
addr_code `snocOL` LD size dst addr
return (Any size code)
where size = cmmTypeSize pk
import PPC.Cond
import Instruction
import Size
+import TargetReg
import RegClass
import Reg
ppc_mkSpillInstr reg delta slot
= let off = spillSlotToOffset slot
in
- let sz = case regClass reg of
+ let sz = case targetClassOfReg reg of
RcInteger -> II32
RcDouble -> FF64
_ -> panic "PPC.Instr.mkSpillInstr: no match"
ppc_mkLoadInstr reg delta slot
= let off = spillSlotToOffset slot
in
- let sz = case regClass reg of
+ let sz = case targetClassOfReg reg of
RcInteger -> II32
RcDouble -> FF64
_ -> panic "PPC.Instr.mkLoadInstr: no match"
import Size
import Reg
import RegClass
+import TargetReg
import BlockId
import Cmm
| reg1 == reg2 = empty
| otherwise = hcat [
char '\t',
- case regClass reg1 of
+ case targetClassOfReg reg1 of
RcInteger -> ptext (sLit "mr")
_ -> ptext (sLit "fmr"),
char '\t',
-----------------------------------------------------------------------------
module PPC.RegInfo (
- mkVReg,
-
JumpDest,
canShortcut,
shortcutJump,
- shortcutStatic,
- regDotColor
+ shortcutStatic
)
where
import PPC.Regs
import PPC.Instr
-import RegClass
-import Reg
-import Size
import BlockId
import Cmm
import CLabel
import Outputable
-import Unique
-
-mkVReg :: Unique -> Size -> Reg
-mkVReg u size
- | not (isFloatSize size) = RegVirtual $ VirtualRegI u
- | otherwise
- = case size of
- FF32 -> RegVirtual $ VirtualRegD u
- FF64 -> RegVirtual $ VirtualRegD u
- _ -> panic "mkVReg"
-
-
-
data JumpDest = DestBlockId BlockId | DestImm Imm
Just (DestImm (ImmCLbl lbl)) -> lbl
_other -> panic "shortBlockId"
-
-
-regDotColor :: Reg -> SDoc
-regDotColor reg
- = case regClass reg of
- RcInteger -> text "blue"
- RcFloat -> text "red"
- RcDouble -> text "green"
-- -----------------------------------------------------------------------------
module PPC.Regs (
+ -- squeeze functions
+ virtualRegSqueeze,
+ realRegSqueeze,
+
+ mkVirtualReg,
+ regDotColor,
+
-- immediates
Imm(..),
strImmLit,
allArgRegs,
callClobberedRegs,
allMachRegNos,
- regClass,
+ classOfRealReg,
showReg,
-- machine specific
import Reg
import RegClass
+import Size
import CgUtils ( get_GlobalReg_addr )
import BlockId
import Cmm
import CLabel ( CLabel )
+import Unique
+
import Pretty
-import Outputable ( Outputable(..), pprPanic, panic )
+import Outputable ( panic, SDoc )
import qualified Outputable
import Constants
import FastBool
+import FastTypes
import Data.Word ( Word8, Word16, Word32 )
import Data.Int ( Int8, Int16, Int32 )
+-- squeese functions for the graph allocator -----------------------------------
+
+-- | regSqueeze_class reg
+-- Calculuate the maximum number of register colors that could be
+-- denied to a node of this class due to having this reg
+-- as a neighbour.
+--
+{-# INLINE virtualRegSqueeze #-}
+virtualRegSqueeze :: RegClass -> VirtualReg -> FastInt
+virtualRegSqueeze cls vr
+ = case cls of
+ RcInteger
+ -> case vr of
+ VirtualRegI{} -> _ILIT(1)
+ VirtualRegHi{} -> _ILIT(1)
+ VirtualRegD{} -> _ILIT(0)
+ VirtualRegF{} -> _ILIT(0)
+
+ -- We don't use floats on this arch, but we can't
+ -- return error because the return type is unboxed...
+ RcFloat
+ -> case vr of
+ VirtualRegI{} -> _ILIT(0)
+ VirtualRegHi{} -> _ILIT(0)
+ VirtualRegD{} -> _ILIT(0)
+ VirtualRegF{} -> _ILIT(0)
+
+ RcDouble
+ -> case vr of
+ VirtualRegI{} -> _ILIT(0)
+ VirtualRegHi{} -> _ILIT(0)
+ VirtualRegD{} -> _ILIT(1)
+ VirtualRegF{} -> _ILIT(0)
+
+
+{-# INLINE realRegSqueeze #-}
+realRegSqueeze :: RegClass -> RealReg -> FastInt
+realRegSqueeze cls rr
+ = case cls of
+ RcInteger
+ -> case rr of
+ RealRegSingle regNo
+ | regNo < 32 -> _ILIT(1) -- first fp reg is 32
+ | otherwise -> _ILIT(0)
+
+ RealRegPair{} -> _ILIT(0)
+
+ -- We don't use floats on this arch, but we can't
+ -- return error because the return type is unboxed...
+ RcFloat
+ -> case rr of
+ RealRegSingle regNo
+ | regNo < 32 -> _ILIT(0)
+ | otherwise -> _ILIT(0)
+
+ RealRegPair{} -> _ILIT(0)
+
+ RcDouble
+ -> case rr of
+ RealRegSingle regNo
+ | regNo < 32 -> _ILIT(0)
+ | otherwise -> _ILIT(1)
+
+ RealRegPair{} -> _ILIT(0)
+
+mkVirtualReg :: Unique -> Size -> VirtualReg
+mkVirtualReg u size
+ | not (isFloatSize size) = VirtualRegI u
+ | otherwise
+ = case size of
+ FF32 -> VirtualRegD u
+ FF64 -> VirtualRegD u
+ _ -> panic "mkVirtualReg"
+
+regDotColor :: RealReg -> SDoc
+regDotColor reg
+ = case classOfRealReg reg of
+ RcInteger -> Outputable.text "blue"
+ RcFloat -> Outputable.text "red"
+ RcDouble -> Outputable.text "green"
+
+
-- immediates ------------------------------------------------------------------
data Imm
= ImmInt Int
allMachRegNos = [0..63]
-{-# INLINE regClass #-}
-regClass :: Reg -> RegClass
-regClass (RegVirtual (VirtualRegI _)) = RcInteger
-regClass (RegVirtual (VirtualRegHi _)) = RcInteger
-regClass (RegVirtual (VirtualRegF u)) = pprPanic ("regClass(ppc):VirtualRegF ") (ppr u)
-regClass (RegVirtual (VirtualRegD _)) = RcDouble
-
-regClass (RegReal (RealRegSingle i))
+{-# INLINE classOfRealReg #-}
+classOfRealReg :: RealReg -> RegClass
+classOfRealReg (RealRegSingle i)
| i < 32 = RcInteger
| otherwise = RcDouble
-regClass (RegReal (RealRegPair{}))
+classOfRealReg (RealRegPair{})
= panic "regClass(ppr): no reg pairs on this architecture"
showReg :: RegNo -> String
-- allocatableRegs is allMachRegNos with the fixed-use regs removed.
-- i.e., these are the regs for which we are prepared to allow the
-- register allocator to attempt to map VRegs to.
-allocatableRegs :: [RegNo]
+allocatableRegs :: [RealReg]
allocatableRegs
= let isFree i = isFastTrue (freeReg i)
- in filter isFree allMachRegNos
+ in map RealRegSingle $ filter isFree allMachRegNos
noFreeRegs :: FreeRegs
noFreeRegs = FreeRegs 0 0
-releaseReg :: RegNo -> FreeRegs -> FreeRegs
-releaseReg r (FreeRegs g f)
+releaseReg :: RealReg -> FreeRegs -> FreeRegs
+releaseReg (RealRegSingle r) (FreeRegs g f)
| r > 31 = FreeRegs g (f .|. (1 `shiftL` (fromIntegral r - 32)))
| otherwise = FreeRegs (g .|. (1 `shiftL` fromIntegral r)) f
+
+releaseReg _ _
+ = panic "RegAlloc.Linear.PPC.releaseReg: bad reg"
initFreeRegs :: FreeRegs
initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
-getFreeRegs :: RegClass -> FreeRegs -> [RegNo] -- lazilly
+getFreeRegs :: RegClass -> FreeRegs -> [RealReg] -- lazilly
getFreeRegs cls (FreeRegs g f)
| RcDouble <- cls = go f (0x80000000) 63
| RcInteger <- cls = go g (0x80000000) 31
| otherwise = pprPanic "RegAllocLinear.getFreeRegs: Bad register class" (ppr cls)
where
go _ 0 _ = []
- go x m i | x .&. m /= 0 = i : (go x (m `shiftR` 1) $! i-1)
+ go x m i | x .&. m /= 0 = RealRegSingle i : (go x (m `shiftR` 1) $! i-1)
| otherwise = go x (m `shiftR` 1) $! i-1
-allocateReg :: RegNo -> FreeRegs -> FreeRegs
-allocateReg r (FreeRegs g f)
+allocateReg :: RealReg -> FreeRegs -> FreeRegs
+allocateReg (RealRegSingle r) (FreeRegs g f)
| r > 31 = FreeRegs g (f .&. complement (1 `shiftL` (fromIntegral r - 32)))
| otherwise = FreeRegs (g .&. complement (1 `shiftL` fromIntegral r)) f
-
+allocateReg _ _
+ = panic "RegAlloc.Linear.PPC.allocateReg: bad reg"
#elif powerpc_TARGET_ARCH
import qualified PPC.Regs as PPC
-import qualified PPC.RegInfo as PPC
#elif sparc_TARGET_ARCH
import qualified SPARC.Regs as SPARC
#include "nativeGen/NCG.h"
#include "HsVersions.h"
-import X86.Regs
import Size
import Reg
#if i386_TARGET_ARCH || x86_64_TARGET_ARCH
import UniqFM
+import X86.Regs
#endif
VirtualRegD{} -> _ILIT(1)
VirtualRegF{} -> _ILIT(0)
-
+realRegSqueeze :: RegClass -> RealReg -> FastInt
#if defined(i386_TARGET_ARCH)
{-# INLINE realRegSqueeze #-}
-realRegSqueeze :: RegClass -> RealReg -> FastInt
-
realRegSqueeze cls rr
= case cls of
RcInteger
RealRegPair{} -> _ILIT(0)
#else
-realRegSqueeze = _ILIT(0)
+realRegSqueeze _ _ = _ILIT(0)
#endif
projects / ghc-hetmet.git / commitdiff