1 Project(#fileName:->'V:\slipway\bitstreams\slipway.apj' #prjName:->'slipway.apj' #prjDir:->'v:\slipway\bitstreams' #parts:->PartList(#parts:->OrderedCollection(PartInstance(#name:->'U1' #part:->
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2 Part(#partCode:->'AT94K10-25DQC' #plugIn:->1.1 #properties:->PartProperties(#application:->'Commercial' #package:->'208PQFP' #productFamily:->'Atmel-FPSLIC' #architecture:->'Atmel-AT94K' #speedGrade:->'-25') #toolFlows:->ToolFlows(
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3 ToolFlow(#name:->'Mentor-VHDL' #tools:->List(
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4 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
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5 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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6 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
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7 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'VHDL File')))
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8 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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9 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
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10 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assemble file')
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11 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
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12 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
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13 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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14 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
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15 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl Files')))
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16 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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17 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
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18 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file')))
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19 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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20 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
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21 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif file')))
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22 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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23 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
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24 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file')))
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25 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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26 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
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27 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file')))
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28 #windowsDescrAsText:->'VHDL Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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29 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
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30 DesignFile(#path:->'%DESIGN_DIRECTORY%' #ext:->'obj' #descriptionToText:->'Object Files')))
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31 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl')
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32 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
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33 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
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34 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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35 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
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36 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
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37 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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38 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
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39 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
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40 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
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41 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
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42 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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43 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
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44 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
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45 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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46 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
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47 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
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48 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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49 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
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50 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
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51 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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52 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
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53 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
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54 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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55 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
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56 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
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57 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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58 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
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59 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
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60 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl')) #imagesList:->
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62 PartImage(#text:->'AT94K FPGA Core: The AT94K core contains array of 8-sided core cells which implements ultra fast design, without using any busing resources. This core is capable of implementing Cache logic and the inbuild FreeRAM can implements RAM without using logic resources.' #imageName:->'94k10.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection('Mentor-VHDL'->
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63 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
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64 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'vhd' #descriptionToText:->'Vhdl file')))
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65 #windowsDescrAsText:->'VHDL Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#true #toolBarIcon:->'' #visibleFromSymbol:->#false) 'Mentor-VHDL'->
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66 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
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67 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif file')))
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68 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#true #toolBarIcon:->'' #visibleFromSymbol:->#true)) #topLeftX:->29 #topLeftY:->30 #rightBottomX:->196 #rightBottomY:->220 #toolBarGrName:->'')
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69 PartImage(#text:->'FPGA West IOs: The west side IOs are 3.3v and 33 MHz PCI compliant. All IO pads are registered IOs and can be programmed indivitually.' #imageName:->'westio.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->0 #topLeftY:->30 #rightBottomX:->21 #rightBottomY:->259 #toolBarGrName:->'')
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70 PartImage(#text:->'FPGA South IOs: The south side IOs are 3.3v and 33 MHz PCI compliant. All IO pads are registered IOs and can be programmed indivitually.' #imageName:->'southio.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->30 #topLeftY:->230 #rightBottomX:->220 #rightBottomY:->251 #toolBarGrName:->'')
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71 PartImage(#text:->'FPGA North IOs: The north side IOs are 3.3v and 33 MHz PCI compliant. All IO pads are registered IOs and can be programmed indivitually.' #imageName:->'northio.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->30 #topLeftY:->0 #rightBottomX:->199 #rightBottomY:->21 #toolBarGrName:->'')
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72 PartImage(#text:->'Dual port Data SRAM interface: This Data SRAM interface component define the interface between the FPGA Core and the data SRAM inside the AVR . The FPGA core can directly access the data SRAM without interrupting AVR microcontroller.' #imageName:->'sram.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->196 #topLeftY:->157 #rightBottomX:->224 #rightBottomY:->220 #toolBarGrName:->'')
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73 PartImage(#text:->'AVR Interface: This AVR interface component define the interface between the AVR CPU and FPGA Core. The FPGA core can not directly interact with AVR and its peripheral, it has to use the AVR bus architecture to interact with them. ' #imageName:->'avrbus.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->196 #topLeftY:->30 #rightBottomX:->223 #rightBottomY:->97 #toolBarGrName:->'')
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74 PartImage(#text:->'AVR CPU: The AVR CPU is a 8-bit RISC microcontroller and it can executes over 30 MIPS. The AVR data bus interfaces directly into the FPGA and treats the FPGA as a large I/O device and can program the FPGA on-the-fly to create Cache logic configuration.' #imageName:->'avrcpu.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->33 #rightBottomX:->290 #rightBottomY:->77 #toolBarGrName:->'')
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75 PartImage(#text:->'UART1: AVR microcontroller has two programmable Serial Universal Asynchronous Receiver and Transmitter. These serial data ports are used to communicate with external serial input/output devices.' #imageName:->'uart1.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->300 #topLeftY:->35 #rightBottomX:->340 #rightBottomY:->77 #toolBarGrName:->'')
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76 PartImage(#text:->'UART2: AVR microcontroller has two programmable Serial Universal Asynchronous Receiver and Transmitter(UART). These serial data ports are used to communicate with external serial input/output devices.' #imageName:->'uart2.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->350 #topLeftY:->35 #rightBottomX:->390 #rightBottomY:->77 #toolBarGrName:->'')
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77 PartImage(#text:->'Two wire serial interface: AVR support Insdustry standard two-wire interface. This serial bus is a bi-directional two-wire serial communication bus and it will carry information between the ICs connected to them.' #imageName:->'i2c.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->400 #topLeftY:->35 #rightBottomX:->450 #rightBottomY:->77 #toolBarGrName:->'')
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78 PartImage(#text:->'Program SRAM: This Program SRAM is used by the AVR RISC microcontroller for program instruction storage. During configuration download, the configuration logic load the program instructions in to this SRAM. The FPGA core user logic can not directly access this SRAM.' #imageName:->'progsram.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->251 #topLeftY:->107 #rightBottomX:->350 #rightBottomY:->150 #toolBarGrName:->'')
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79 PartImage(#text:->'Timer/Counter2: The Timer/Counter2 is a 8-bit general purpose counter and it has its own prescaling timer. This counter can be reset by setting the corresponding control bits in the Special Functions IO register.' #imageName:->'count2.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->358 #topLeftY:->107 #rightBottomX:->400 #rightBottomY:->150 #toolBarGrName:->'')
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80 PartImage(#text:->'WatchDog Timer: The WatchDog Timer is clocked from a separate on-chip oscillator which runs at 1MHz. The watchdog timer reset interval can be adjusted by controlling the watchdog Timer prescaler.' #imageName:->'wdog.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->408 #topLeftY:->107 #rightBottomX:->450 #rightBottomY:->150 #toolBarGrName:->'')
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81 PartImage(#text:->'Data SRAM: This dual port data SRAM resides inside the AVR and it is used for data storage. The FPGA user logic can directly access this data SRAM without interrupting AVR bus. Both FPGA and AVR have full read and write access to this SRAM.' #imageName:->'dpram.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->180 #rightBottomX:->335 #rightBottomY:->222 #toolBarGrName:->'')
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82 PartImage(#text:->'Timer/Counter0: The Timer/Counter0 is a 8-bit general purpose counter and it has its own prescaling timer. This counter can be reset by setting the corresponding control bits in the Special Functions IO register.' #imageName:->'count1.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->346 #topLeftY:->180 #rightBottomX:->388 #rightBottomY:->222 #toolBarGrName:->'')
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83 PartImage(#text:->'Timer/Counter1: The Timer/Counter1 is a 16-bit general purpose counter and it has its own prescaling timer. This counter can be reset by setting the corresponding control bits in the Special Functions IO register.' #imageName:->'count3.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->396 #topLeftY:->180 #rightBottomX:->448 #rightBottomY:->222 #toolBarGrName:->'')
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84 PartImage(#text:->'Port D: Port D is an 8-bit parallel bidirectional IO port.' #imageName:->'portd.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->473 #topLeftY:->33 #rightBottomX:->503 #rightBottomY:->95 #toolBarGrName:->'')
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85 PartImage(#text:->'Port E: Port E is an 8-bit parallel bidirectional IO port.' #imageName:->'porte.bmp' #colorName:->'black' #actionName:->'' #webPage:->'%FIGARO_HOME%\examples\at94k\Resources\samplecode.htm' #toolsRestore:->OrderedCollection() #topLeftX:->473 #topLeftY:->113 #rightBottomX:->503 #rightBottomY:->175 #toolBarGrName:->'')
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86 PartImage(#text:->'bus1' #imageName:->'bus1.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->221 #topLeftY:->33 #rightBottomX:->250 #rightBottomY:->235 #toolBarGrName:->'')
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87 PartImage(#text:->'bus2' #imageName:->'bus2.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->77 #rightBottomX:->450 #rightBottomY:->110 #toolBarGrName:->'')
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88 PartImage(#text:->'bus3' #imageName:->'bus3.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->250 #topLeftY:->162 #rightBottomX:->450 #rightBottomY:->182 #toolBarGrName:->'')
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89 PartImage(#text:->'bus4' #imageName:->'bus4.bmp' #colorName:->'black' #actionName:->'' #webPage:->'' #toolsRestore:->OrderedCollection() #topLeftX:->450 #topLeftY:->42 #rightBottomX:->480 #rightBottomY:->183 #toolBarGrName:->''))) #tools:->OrderedCollection(ToolInstance(#name:->'AT94K Device Options' #tool:->
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90 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
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91 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:->
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92 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
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93 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
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94 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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95 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
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96 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
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97 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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98 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
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99 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
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100 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
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101 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
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102 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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103 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
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104 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
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105 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
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106 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
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107 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
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108 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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109 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
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110 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
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111 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
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112 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
113 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
114 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
115 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
116 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
117 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
118 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
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119 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
120 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'HDL Synthesis' #tool:->
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121 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
122 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
123 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:->
\r
124 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
125 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
126 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
127 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
128 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
129 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
130 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
131 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
132 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
133 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
134 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
135 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
136 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
137 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
138 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
139 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
140 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
141 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
142 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
143 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
144 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
145 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
146 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
147 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
148 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
149 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
150 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
151 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
152 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection(DesignFileInstance(#fileName:->'v:\slipway\bitstreams\stupid.v' #designFile:->
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153 DesignFile(#path:->'v:\slipway\bitstreams\' #ext:->'v' #descriptionToText:->'Verilog File')))) ToolInstance(#name:->'Software Compiler' #tool:->
\r
154 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
155 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
156 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
157 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
158 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:->
\r
159 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
160 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
161 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
162 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
163 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
164 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
165 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
166 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
167 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
168 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
169 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
170 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
171 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
172 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
173 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
174 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
175 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
176 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
177 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
178 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
179 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
180 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
181 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
182 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
183 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
184 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
185 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
186 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
187 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'AVR-FPGA Interface' #tool:->
\r
188 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
189 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
190 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:->
\r
191 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
192 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
193 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
194 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
195 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
196 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
197 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
198 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
199 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
200 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
201 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
202 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
203 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
204 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
205 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
206 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
207 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
208 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
209 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
210 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
211 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
212 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
213 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
214 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
215 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
216 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
217 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
218 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
219 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'Pre-layout Coverification' #tool:->
\r
220 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
221 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
222 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:->
\r
223 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
224 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
225 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
226 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
227 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
228 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
229 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
230 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
231 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
232 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
233 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
234 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
235 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
236 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
237 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
238 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
239 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
240 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
241 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
242 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
243 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
244 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
245 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
246 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
247 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
248 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
249 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
250 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
251 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection(DesignFileInstance(#fileName:->'v:\slipway\bitstreams\stupid_pretb.v' #designFile:->
\r
252 DesignFile(#path:->'v:\slipway\bitstreams\' #ext:->'v' #descriptionToText:->'')))) ToolInstance(#name:->'FPGA Place and Router' #tool:->
\r
253 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
254 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
255 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:->
\r
256 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
257 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
258 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
259 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
260 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
261 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
262 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
263 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
264 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
265 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
266 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
267 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
268 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
269 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
270 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
271 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
272 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
273 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
274 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
275 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
276 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
277 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
278 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
279 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
280 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
281 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
282 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
283 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
284 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'stupid' #designFiles:->OrderedCollection(DesignFileInstance(#fileName:->'v:\slipway\bitstreams\stupid.edf' #designFile:->
\r
285 DesignFile(#path:->'v:\slipway\bitstreams\' #ext:->'edf' #descriptionToText:->'')))) ToolInstance(#name:->'Post-layout Coverification' #tool:->
\r
286 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
287 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
288 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true) #toolFlow:->
\r
289 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
290 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
291 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
292 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
293 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
294 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
295 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
296 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
297 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
298 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
299 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
300 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
301 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
302 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
303 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
304 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
305 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
306 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
307 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
308 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
309 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
310 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
311 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
312 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
313 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
314 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
315 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
316 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
317 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'stupid' #designFiles:->OrderedCollection()) ToolInstance(#name:->'HDL Simulator - ModelSim' #tool:->
\r
318 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
319 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
320 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:->
\r
321 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
322 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
323 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
324 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
325 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
326 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
327 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
328 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
329 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
330 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
331 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
332 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
333 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
334 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
335 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
336 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
337 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
338 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
339 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
340 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
341 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
342 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
343 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
344 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
345 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
346 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
347 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
348 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
349 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection()) ToolInstance(#name:->'Software Debugger' #tool:->
\r
350 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
351 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
352 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false) #toolFlow:->
\r
353 ToolFlow(#name:->'Mentor-Verilog' #tools:->List(
\r
354 Tool(#name:->'AT94K Device Options' #windowsCommand:->Command(#commandLine:->'$at94koptions' #designFiles:->List())
\r
355 #windowsDescrAsText:->'AT94K Device Options' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
356 Tool(#name:->'HDL Synthesis' #windowsCommand:->Command(#commandLine:->'at94kleonardo.pcl' #designFiles:->List(
\r
357 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
358 #windowsDescrAsText:->'HDL Design Entry and synthesis' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
359 Tool(#name:->'Software Compiler' #windowsCommand:->Command(#commandLine:->'wavrasm' #designFiles:->List(
\r
360 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'asm' #descriptionToText:->'Assembly File')
\r
361 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'c' #descriptionToText:->'''C'' Files')
\r
362 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
363 #windowsDescrAsText:->'Software Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
364 Tool(#name:->'AVR-FPGA Interface' #windowsCommand:->Command(#commandLine:->'$at94kavrfpgainterface' #designFiles:->List(
\r
365 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog File')))
\r
366 #windowsDescrAsText:->'Define AVR and FPGA Interface and Generate the functional test bench model.' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
367 Tool(#name:->'Pre-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kprelayoutcoverify' #designFiles:->List(
\r
368 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
369 #windowsDescrAsText:->'Pre-layout Hardware and Software coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
370 Tool(#name:->'FPGA Place and Router' #windowsCommand:->Command(#commandLine:->'$at94kfigaro' #designFiles:->List(
\r
371 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'edf' #descriptionToText:->'edif File')))
\r
372 #windowsDescrAsText:->'FPGA Place and Router' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
373 Tool(#name:->'Post-layout Coverification' #windowsCommand:->Command(#commandLine:->'$at94kpostlayoutcoverify' #designFiles:->List(
\r
374 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
375 #windowsDescrAsText:->'Post-layout Hardware and Software Coverification' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#true)
\r
376 Tool(#name:->'HDL Simulator - ModelSim' #windowsCommand:->Command(#commandLine:->'%FIGARO_HOME%\modeltech\win32aoem\modelsim.exe' #designFiles:->List(
\r
377 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'v' #descriptionToText:->'Verilog file')))
\r
378 #windowsDescrAsText:->'Verilog Design Compiler' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)
\r
379 Tool(#name:->'Software Debugger' #windowsCommand:->Command(#commandLine:->'avrstudio' #designFiles:->List(
\r
380 DesignFile(#path:->'%DESIGN_DIRECTORY%\' #ext:->'obj' #descriptionToText:->'Object Files')))
\r
381 #windowsDescrAsText:->'Software Debugger' #unixCommand:->Command(#commandLine:->'' #designFiles:->List()) #unixDescrAsText:->'' #isPartImageToolFromSymbol:->#false #toolBarIcon:->'' #visibleFromSymbol:->#false)) #descriptionToText:->'Hardware/Software coverification' #flowParcel:->'flow1.pcl') #designDirectory:->'v:\slipway\bitstreams' #designName:->'' #designFiles:->OrderedCollection())) #version:->1.1 #properties:->Dictionary(#FREQ->2 #B19->false #B4->false #SRAMWRITE->false #COMMANDFILENAME->'' #TESTBENCHFILE->'v:\stupid\stupid_pretb.v' #B18->false #USERLIBRARYLIST->List('v:\stupid\user94k.lib') #FPGABITSTREAM->false #FPGABITSTREAMNAME->'v:\stupid\stupid.bst' #B20->false #B30->true #LOADDATARAM->false #AVRPORTEDRIVE->1 #B16->false #COMBINEDBITSTREAMFILENAME->'v:\slipway\build\slipway_drone_complete.bst' #DATARAMFILETYPE->'Atmel Text Format' #B31->true #EXTINT3->1 #UART1PINS->1 #PROTECTAVRPROGRAMSRAM->false #GCK6SOURCE->#avr #AVRHEXFILE->true #OPENTYPE->#EDIF #B17->false #AVRRESETPINDISABLE->true #EXTINT1->1 #FGDFILENAME->'' #B25->false #AVRHEXFILENAME->'v:\slipway\build\slipway_drone.hex' #EDIFFILENAME->'V:\stupid\stupid.edf' #UART0PINS->0 #TOSCPADBIASRESISTOR->false #EXTINT2->1 #CACHEWRITE->true #EXECUTECOMMANDFILE->false #DENSITY->'1M' #PROGRAMSIZE->16 #XTALPADBIASRESISTOR->true #B2->true #B6->false #AVRPORTDDRIVE->1 #GENERATETESTBENCH->true #XTAL2PAD->false #B24->false #CPS->false #JTAG->true #B13->false #USERDEFINEDFILENAME->'' #EXTINT0->1 #PROTECTAVRBOOTBLOCK->false #B27->true #B3->false #B26->true #B21->false)))))
projects / slipway.git / blob