3 == Ports ===========================================================
10 percolate up: gpio_led_0 1
11 percolate up: gpio_led_1 1
12 percolate up: gpio_led_2 1
13 percolate up: gpio_led_3 1
15 percolate inout: ddr2_dq 64
16 percolate up: ddr2_a 13
17 percolate up: ddr2_ba 2
18 percolate up: ddr2_ras_n 1
19 percolate up: ddr2_cas_n 1
20 percolate up: ddr2_we_n 1
21 percolate up: ddr2_cs_n 1
22 percolate up: ddr2_odt 1
23 percolate up: ddr2_cke 1
24 percolate up: ddr2_dm 8
25 percolate up: phy_init_done 1
26 percolate inout: ddr2_dqs 8
27 percolate inout: ddr2_dqs_n 8
28 percolate up: ddr2_ck 2
29 percolate up: ddr2_ck_n 2
31 == TeX ==============================================================
33 == Fleeterpreter ====================================================
34 public void service() { }
35 == FleetSim ==============================================================
37 == FPGA ==============================================================
40 percolate inout: ddr2_dq 8
41 percolate up: ddr2_a 15
42 percolate up: ddr2_ba 3
43 percolate up: ddr2_ras_n 1
44 percolate up: ddr2_cas_n 1
45 percolate up: ddr2_we_n 1
46 percolate up: ddr2_cs_n 1
47 percolate up: ddr2_odt 1
48 percolate up: ddr2_cke 1
49 percolate up: ddr2_dm 1
50 percolate up: phy_init_done 1
51 percolate inout: ddr2_dqs 1
52 percolate inout: ddr2_dqs_n 1
53 percolate up: ddr2_ck 1
54 percolate up: ddr2_ck_n 1
57 //NET "sys_clk_p" LOC = "H17" ; #Bank 3
58 //NET "sys_clk_n" LOC = "H18" ; #Bank 3
59 //NET "clk200_p" LOC = "K17" ; #Bank 3
60 //NET "clk200_n" LOC = "L18" ; #Bank 3
61 //NET "sys_rst_n" LOC = "L24" ; #Bank 19
63 /*******************************************************************************
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91 // The following must be inserted into your Verilog file for this
92 // core to be instantiated. Change the instance name and port connections
93 // (in parentheses) to your own signal names.
95 //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
102 .BANK_WIDTH(2), // # of memory bank addr bits.
103 .CKE_WIDTH(1), // # of memory clock enable outputs.
104 .CLK_WIDTH(2), // # of clock outputs.
105 .COL_WIDTH(10), // # of memory column bits.
106 .CS_NUM(1), // # of separate memory chip selects.
107 .CS_WIDTH(1), // # of total memory chip selects.
108 .CS_BITS(0), // set to log2(CS_NUM) (rounded up).
109 .DM_WIDTH(8), // # of data mask bits.
110 .DQ_WIDTH(64), // # of data width.
111 .DQ_PER_DQS(8), // # of DQ data bits per strobe.
112 .DQS_WIDTH(8), // # of DQS strobes.
113 .DQ_BITS(6), // set to log2(DQS_WIDTH*DQ_PER_DQS).
114 .DQS_BITS(3), // set to log2(DQS_WIDTH).
115 .ODT_WIDTH(1), // # of memory on-die term enables.
116 .ROW_WIDTH(13), // # of memory row and # of addr bits.
117 .ADDITIVE_LAT(0), // additive write latency.
118 .BURST_LEN(4), // burst length (in double words).
119 .BURST_TYPE(0), // burst type (=0 seq; =1 interleaved).
120 .CAS_LAT(4), // CAS latency.
121 .ECC_ENABLE(0), // enable ECC (=1 enable).
122 .APPDATA_WIDTH(128), // # of usr read/write data bus bits.
123 .MULTI_BANK_EN(1), // Keeps multiple banks open. (= 1 enable).
124 .TWO_T_TIME_EN(1), // 2t timing for unbuffered dimms.
125 .ODT_TYPE(1), // ODT (=0(none),=1(75),=2(150),=3(50)).
126 .REDUCE_DRV(0), // reduced strength mem I/O (=1 yes).
127 .REG_ENABLE(0), // registered addr/ctrl (=1 yes).
128 .TREFI_NS(7800), // auto refresh interval (ns).
129 .TRAS(40000), // active->precharge delay.
130 .TRCD(15000), // active->read/write delay.
131 .TRFC(127500), // refresh->refresh, refresh->active delay.
132 .TRP(15000), // precharge->command delay.
133 .TRTP(7500), // read->precharge delay.
134 .TWR(15000), // used to determine write->precharge.
135 .TWTR(7500), // write->read delay.
136 .HIGH_PERFORMANCE_MODE("TRUE"), // # = TRUE, the IODELAY performance mode is set to high.
137 // # = FALSE, the IODELAY performance mode is set to low.
138 .SIM_ONLY(0), // = 1 to skip SDRAM power up delay.
139 .DEBUG_EN(0), // Enable debug signals/controls.
140 // When this parameter is changed from 0 to 1,
141 // make sure to uncomment the coregen commands
142 // in ise_flow.bat or create_ise.bat files in
144 .CLK_PERIOD(5000), // Core/Memory clock period (in ps).
145 .DQS_IO_COL(16'b0000000000000000), // I/O column location of DQS groups
146 // (=0, left; =1 center, =2 right).
147 //.DQ_IO_MS(64'b10100101_10100101_10100101_10100101_10100101_10100101_10100101_10100101),
148 .DQ_IO_MS(64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100),
149 // Master/Slave location of DQ I/O (=0 slave).
150 .CLK_TYPE("SINGLE_ENDED"), // # = "DIFFERENTIAL " ->; Differential input clocks ,
151 // # = "SINGLE_ENDED" -> Single ended input clocks.
152 .DLL_FREQ_MODE("HIGH"), // DCM Frequency range.
153 .RST_ACT_LOW(1) // =1 for active low reset, =0 for active high.
157 .idly_clk_200 (clk200_p),
163 .ddr2_ras_n (ddr2_ras_n),
164 .ddr2_cas_n (ddr2_cas_n),
165 .ddr2_we_n (ddr2_we_n),
166 .ddr2_cs_n (ddr2_cs_n),
167 .ddr2_odt (ddr2_odt),
168 .ddr2_cke (ddr2_cke),
170 .ddr2_dqs (ddr2_dqs),
171 .ddr2_dqs_n (ddr2_dqs_n),
173 .ddr2_ck_n (ddr2_ck_n),
175 .phy_init_done (gpio_led_0),
177 .app_wdf_afull (gpio_led_1),
178 .app_af_afull (gpio_led_2),
179 .rd_data_valid (gpio_led_3),
181 .app_wdf_wren (1'b1),
182 .app_af_wren (app_af_wren),
183 .app_af_addr (app_af_addr),
184 .app_af_cmd (app_af_cmd),
186 .rd_data_fifo_out (rd_data_fifo_out),
187 .app_wdf_data (app_wdf_data),
188 .app_wdf_mask_data (app_wdf_mask_data)
192 DCM // 200Mhz DDR clock
196 .CLKIN_PERIOD("10 ns")
199 .CLKFB (clk200_p_fb),
201 .CLKFX180 (clk200_p),
206 always @(posedge clk) begin
218 if (`out_empty) begin
222 if (DataOutReady && DataOutValid && `out_empty) begin
223 out_d <= { 1'b0, DataOut[`WORDWIDTH-1:0] };
227 end else if (DataOutReady && CommandReady && DataInReady && `out_empty) begin
228 if (`inAddrWrite_full && `inDataWrite_full) begin
231 CommandAddress <= inAddrWrite_d;
235 out_d <= { 1'b1, 37'b0 };
238 end else if (`inAddrRead_full) begin
240 CommandAddress <= inAddrRead_d;
251 == Test ==============================================================
281 == Constants ========================================================
283 == Contributors =========================================================
284 Adam Megacz <megacz@cs.berkeley.edu>