Adam Megacz [Tue, 21 Jul 2009 04:54:05 +0000 (04:54 +0000)]
works speculatively with predCond3
Adam Megacz [Tue, 21 Jul 2009 04:36:47 +0000 (04:36 +0000)]
works (again)
Adam Megacz [Tue, 21 Jul 2009 01:36:14 +0000 (01:36 +0000)]
even yet more logic refactoring
Adam Megacz [Tue, 21 Jul 2009 01:35:18 +0000 (01:35 +0000)]
even yet more logic refactoring
Adam Megacz [Tue, 21 Jul 2009 01:34:42 +0000 (01:34 +0000)]
even yet more logic refactoring
Adam Megacz [Tue, 21 Jul 2009 01:30:39 +0000 (01:30 +0000)]
more logic refactoring
Adam Megacz [Tue, 21 Jul 2009 01:28:33 +0000 (01:28 +0000)]
refactored some logic
Adam Megacz [Tue, 21 Jul 2009 01:21:40 +0000 (01:21 +0000)]
removed another unnecessary delay on driver input
Adam Megacz [Tue, 21 Jul 2009 01:12:17 +0000 (01:12 +0000)]
equalized pull-downs in state wire drivers, works
Adam Megacz [Tue, 21 Jul 2009 00:54:22 +0000 (00:54 +0000)]
removed unnecessary delay on driver input, resized transistors and used low-threshold inverrters to compensate
Adam Megacz [Tue, 21 Jul 2009 00:19:06 +0000 (00:19 +0000)]
removed unnecessary delay on keeper input
Adam Megacz [Tue, 21 Jul 2009 00:09:58 +0000 (00:09 +0000)]
removed one stage of delay, changed disable to disableLO
Adam Megacz [Mon, 20 Jul 2009 23:03:23 +0000 (23:03 +0000)]
works in 4/2 GasP, new firing circuit, 60ps/stage
Adam Megacz [Fri, 17 Jul 2009 10:17:15 +0000 (10:17 +0000)]
works
Adam Megacz [Fri, 17 Jul 2009 07:31:00 +0000 (07:31 +0000)]
ok better
Adam Megacz [Fri, 17 Jul 2009 06:49:23 +0000 (06:49 +0000)]
topology tweaks
Adam Megacz [Fri, 17 Jul 2009 06:44:55 +0000 (06:44 +0000)]
works, more delay line shortening
Adam Megacz [Fri, 17 Jul 2009 06:24:31 +0000 (06:24 +0000)]
works, shorter delay line (correction)
Adam Megacz [Fri, 17 Jul 2009 06:24:04 +0000 (06:24 +0000)]
works, shorter delay line
Adam Megacz [Fri, 17 Jul 2009 06:12:13 +0000 (06:12 +0000)]
works, but just barely -- really cutting it close!
Adam Megacz [Fri, 17 Jul 2009 04:52:22 +0000 (04:52 +0000)]
works
Adam Megacz [Fri, 17 Jul 2009 04:36:52 +0000 (04:36 +0000)]
works, took two inverters off of forward conditioning path
Adam Megacz [Fri, 17 Jul 2009 04:22:13 +0000 (04:22 +0000)]
works, tweaked inverter size
Adam Megacz [Fri, 17 Jul 2009 04:16:35 +0000 (04:16 +0000)]
works, slower delay line
Adam Megacz [Fri, 17 Jul 2009 04:13:26 +0000 (04:13 +0000)]
works, shorter delay line
Adam Megacz [Fri, 17 Jul 2009 04:08:22 +0000 (04:08 +0000)]
works, tweaked one transistor size
Adam Megacz [Fri, 17 Jul 2009 03:59:02 +0000 (03:59 +0000)]
works with wire loads
Adam Megacz [Fri, 17 Jul 2009 03:55:01 +0000 (03:55 +0000)]
work with even less delay
Adam Megacz [Fri, 17 Jul 2009 03:39:01 +0000 (03:39 +0000)]
work with less delay
Adam Megacz [Fri, 17 Jul 2009 03:34:20 +0000 (03:34 +0000)]
still works, smarter keepers
Adam Megacz [Fri, 17 Jul 2009 03:24:49 +0000 (03:24 +0000)]
still works
Adam Megacz [Fri, 17 Jul 2009 03:22:07 +0000 (03:22 +0000)]
still works
Adam Megacz [Thu, 16 Jul 2009 19:43:33 +0000 (19:43 +0000)]
cleaned up omegaCounter fire module
Adam Megacz [Thu, 16 Jul 2009 18:44:57 +0000 (18:44 +0000)]
rename tinyCounter to omegaCounter
Adam Megacz [Thu, 16 Jul 2009 18:44:00 +0000 (18:44 +0000)]
tinyCounter: all loads work
Adam Megacz [Tue, 14 Jul 2009 04:50:32 +0000 (04:50 +0000)]
new tinyCounter, uses only 44 transistors per bit
Adam Megacz [Tue, 14 Jul 2009 04:50:05 +0000 (04:50 +0000)]
added tinyCounter.jelib
Adam Megacz [Tue, 14 Jul 2009 04:48:53 +0000 (04:48 +0000)]
add fakeMarinaPadframe to aMarinaM.jelib
Adam Megacz [Tue, 14 Jul 2009 04:48:25 +0000 (04:48 +0000)]
use fakeMarinaPadframe in marina-xml2.bsh
Adam Megacz [Tue, 14 Jul 2009 04:28:15 +0000 (04:28 +0000)]
short together pins to make XML generator work
Adam Megacz [Tue, 14 Jul 2009 04:16:20 +0000 (04:16 +0000)]
fine-tine the print_node_v except-line in cfg
Adam Megacz [Tue, 14 Jul 2009 04:15:57 +0000 (04:15 +0000)]
add extra spice parameters for HSIM in header.hsp
Adam Megacz [Tue, 14 Jul 2009 04:15:00 +0000 (04:15 +0000)]
fix typo in marina-xml1.bsh
Adam Megacz [Tue, 14 Jul 2009 04:14:43 +0000 (04:14 +0000)]
use fakeMarinaPadframe in marina-netlist2.bsh
Adam Megacz [Tue, 14 Jul 2009 04:14:15 +0000 (04:14 +0000)]
switch marina-netlist1.bsh from FileMenu to FileType for Electric 8.10a
Adam Megacz [Tue, 14 Jul 2009 04:13:46 +0000 (04:13 +0000)]
marina-xml2.bsh: add explicit TDI/TDO port names
jlexau [Sun, 14 Jun 2009 02:07:33 +0000 (02:07 +0000)]
added exports to CR block to clean up ERC errors
Adam Megacz [Sat, 13 Jun 2009 20:18:19 +0000 (20:18 +0000)]
shrink logo by one pixel in both dimensions, rotate logo by 180 degrees
jlexau [Sat, 13 Jun 2009 08:29:55 +0000 (08:29 +0000)]
touched edgesM and marina_padframe to clean up library read errors
Adam Megacz [Sat, 13 Jun 2009 02:07:16 +0000 (02:07 +0000)]
update fillM
Adam Megacz [Tue, 9 Jun 2009 20:42:38 +0000 (20:42 +0000)]
test script updates
jlexau [Tue, 9 Jun 2009 17:40:47 +0000 (17:40 +0000)]
added new crTest block to top level
jlexau [Tue, 9 Jun 2009 17:40:24 +0000 (17:40 +0000)]
counter fix from Ivan for scan generator
ac150875 [Tue, 9 Jun 2009 16:55:50 +0000 (16:55 +0000)]
lvs, erc, drc clean
Adam Megacz [Tue, 9 Jun 2009 00:44:46 +0000 (00:44 +0000)]
fix D-flag bug in kessels counter
ac150875 [Mon, 8 Jun 2009 19:07:49 +0000 (19:07 +0000)]
capacitive-resistive measurement
Adam Megacz [Mon, 8 Jun 2009 18:49:04 +0000 (18:49 +0000)]
add tpdn90g18_3.spi
Adam Megacz [Sun, 7 Jun 2009 18:09:27 +0000 (18:09 +0000)]
newest files from ivan
Adam Megacz [Fri, 5 Jun 2009 22:33:31 +0000 (22:33 +0000)]
fixed incorrect instantiation mistake; all tests pass now
jlexau [Fri, 5 Jun 2009 20:48:27 +0000 (20:48 +0000)]
fixed a drc error
jlexau [Fri, 5 Jun 2009 20:27:18 +0000 (20:27 +0000)]
fixed top-level fill cell
jlexau [Fri, 5 Jun 2009 18:57:00 +0000 (18:57 +0000)]
added vdd/gnd exports at corner of esd block
jlexau [Fri, 5 Jun 2009 18:48:31 +0000 (18:48 +0000)]
update from Adam
jlexau [Fri, 5 Jun 2009 18:07:22 +0000 (18:07 +0000)]
updates from Adam, plus DRC fixes
Adam Megacz [Thu, 4 Jun 2009 23:19:33 +0000 (23:19 +0000)]
stuff
jlexau [Thu, 4 Jun 2009 18:03:08 +0000 (18:03 +0000)]
fixed ERC error in pads_north
ac150875 [Tue, 2 Jun 2009 23:38:22 +0000 (23:38 +0000)]
fixed erc errors
jlexau [Tue, 2 Jun 2009 23:37:58 +0000 (23:37 +0000)]
changed config_input to fix DRC/ERC errors
jlexau [Tue, 2 Jun 2009 16:44:36 +0000 (16:44 +0000)]
deleted twinNand{lay} at Ivan's suggestion
Adam Megacz [Tue, 2 Jun 2009 11:31:52 +0000 (11:31 +0000)]
kesselscounter passes ncc, drc
jlexau [Tue, 2 Jun 2009 05:40:40 +0000 (05:40 +0000)]
Created project settings to get the GDS layers correct.
Adam Megacz [Tue, 2 Jun 2009 05:09:44 +0000 (05:09 +0000)]
kesselCounter layout complete, passes NCC and DRC
jlexau [Sat, 30 May 2009 00:08:02 +0000 (00:08 +0000)]
revised dummy exclusion layers for core
jlexau [Fri, 29 May 2009 21:30:09 +0000 (21:30 +0000)]
added Alex's ESD experiment (LVS fixes)
jlexau [Fri, 29 May 2009 08:54:28 +0000 (08:54 +0000)]
adding Alex's ESD experiment to top level
jlexau [Fri, 29 May 2009 08:03:28 +0000 (08:03 +0000)]
latest files from Ivan plus top-level hookup
Adam Megacz [Fri, 29 May 2009 08:03:12 +0000 (08:03 +0000)]
broke out ripple-carry logic into a separate module, broke it down into transistors
Adam Megacz [Fri, 29 May 2009 06:40:11 +0000 (06:40 +0000)]
remove inversion from kessels OLC scan (and special case from test code)
Adam Megacz [Fri, 29 May 2009 06:39:08 +0000 (06:39 +0000)]
simplify ripple-carry logic
Adam Megacz [Fri, 29 May 2009 06:35:34 +0000 (06:35 +0000)]
make test 6 harder
Adam Megacz [Fri, 29 May 2009 06:32:06 +0000 (06:32 +0000)]
test updates for kessels counter
Adam Megacz [Fri, 29 May 2009 06:30:53 +0000 (06:30 +0000)]
proper decoding of kessels OLC scan
Adam Megacz [Fri, 29 May 2009 06:30:21 +0000 (06:30 +0000)]
better debugging messages on ProperStopper
Adam Megacz [Fri, 29 May 2009 06:30:02 +0000 (06:30 +0000)]
add hsim gunk to header.hsp
Adam Megacz [Fri, 29 May 2009 06:28:21 +0000 (06:28 +0000)]
kessels passes all tests, hsim+verilog
ac150875 [Thu, 28 May 2009 21:26:30 +0000 (21:26 +0000)]
added fill
ac150875 [Thu, 28 May 2009 21:22:58 +0000 (21:22 +0000)]
added fill
ac150875 [Thu, 28 May 2009 21:00:12 +0000 (21:00 +0000)]
top level with ivan's fill
ac150875 [Thu, 28 May 2009 20:57:20 +0000 (20:57 +0000)]
top level with ivan's fill
Adam Megacz [Thu, 28 May 2009 06:23:17 +0000 (06:23 +0000)]
updates for kessels counter
Adam Megacz [Thu, 28 May 2009 06:16:40 +0000 (06:16 +0000)]
changes for kesselsCounter, flip initial state of D-flag in verilog
Adam Megacz [Thu, 28 May 2009 06:09:37 +0000 (06:09 +0000)]
checkpoint2: pre-sizing
Adam Megacz [Thu, 28 May 2009 05:32:59 +0000 (05:32 +0000)]
checkpoint1
Adam Megacz [Thu, 28 May 2009 05:21:49 +0000 (05:21 +0000)]
remove now-auto-generated files
Adam Megacz [Thu, 28 May 2009 05:21:09 +0000 (05:21 +0000)]
add verilog/spice generation to marina.bsh
Adam Megacz [Thu, 28 May 2009 05:20:28 +0000 (05:20 +0000)]
kessels bugfixes
Adam Megacz [Thu, 28 May 2009 02:44:18 +0000 (02:44 +0000)]
add useHsim option
Adam Megacz [Thu, 28 May 2009 02:44:00 +0000 (02:44 +0000)]
new marina.xml
Adam Megacz [Thu, 28 May 2009 02:43:47 +0000 (02:43 +0000)]
marina.bsh updates for new scanCellFtaller
ac150875 [Wed, 27 May 2009 21:38:15 +0000 (21:38 +0000)]
top level with ivan's fill