try to re-enable break line in Debug.ship (but doesnt work), add a note about deadlock
[fleet.git] / ships / DDR2.ship
2009-03-07 megaczDDR2 ship: works on ML509
2009-03-01 megaczadd DDR2 controller, generated via MIG
2009-01-25 megaczchange rst to high-active
2009-01-11 megaczremove `flush macro, fold it into `cleanup
2009-01-08 megaczoverhaul of interpreter, update ships to match; "make...
2008-12-30 megaczmove to ml505, import Greg\'s memory controller
2008-11-10 adamadjust ships to use fill/drain/full/empty macros
2008-10-27 adamadd flush support to ships